def __init__(self, entity, name, clock, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) self._can_read = False self._can_write = False # Drive some sensible defaults (setimmediatevalue to avoid x asserts) if hasattr(self.bus, "read"): self.bus.read.setimmediatevalue(0) self._can_read = True if hasattr(self.bus, "write"): self.bus.write.setimmediatevalue(0) v = self.bus.writedata.value v.binstr = "x" * len(self.bus.writedata) self.bus.writedata.value = v self._can_write = True if hasattr(self.bus, "byteenable"): self.bus.byteenable.setimmediatevalue(0) if hasattr(self.bus, "cs"): self.bus.cs.setimmediatevalue(0) v = self.bus.address.value v.binstr = "x" * len(self.bus.address) self.bus.address.setimmediatevalue(v)
def __init__(self, entity: SimHandleBase, name: str, clock: SimHandleBase, **kwargs: Any): BusDriver.__init__(self, entity, name, clock, **kwargs) # Drive some sensible defaults (setimmediatevalue to avoid x asserts) self.bus.AWVALID.setimmediatevalue(0) self.bus.WVALID.setimmediatevalue(0) self.bus.ARVALID.setimmediatevalue(0) self.bus.BREADY.setimmediatevalue(1) self.bus.RREADY.setimmediatevalue(1) # Set the default value (0) for the unsupported signals, which # translate to: # * Transaction IDs to 0 # * Region identifier to 0 # * Normal (non-exclusive) access # * Device non-bufferable access # * Unprivileged, secure data access # * No QoS unsupported_signals = [ "AWID", "AWREGION", "AWLOCK", "AWCACHE", "AWPROT", "AWQOS", "ARID", "ARREGION", "ARLOCK", "ARCACHE", "ARPROT", "ARQOS"] for signal in unsupported_signals: try: getattr(self.bus, signal).setimmediatevalue(0) except AttributeError: pass # Mutex for each channel to prevent contention self.write_address_busy = Lock(name + "_awbusy") self.read_address_busy = Lock(name + "_arbusy") self.write_data_busy = Lock(name + "_wbusy") self.read_data_busy = Lock(name + "_rbusy") self.write_response_busy = Lock(name + "_bbusy")
def __init__(self, entity, name, clock, memory, callback=None, event=None, big_endian=False, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) self.clock = clock self.big_endian = big_endian self.bus.ARREADY.setimmediatevalue(1) self.bus.RVALID.setimmediatevalue(0) self.bus.RLAST.setimmediatevalue(0) self.bus.AWREADY.setimmediatevalue(1) self._memory = memory self.write_address_busy = Lock("%s_wabusy" % name) self.read_address_busy = Lock("%s_rabusy" % name) self.write_data_busy = Lock("%s_wbusy" % name) cocotb.fork(self._read_data()) cocotb.fork(self._write_data())
def __init__(self, entity, name, clock, **kwargs): # config = kwargs.pop('config', {}) BusDriver.__init__(self, entity, name, clock, **kwargs) self.bus.tvalid.value = 0 self.bus.tdata.value = 0 self._keep = False if hasattr(self.bus, "keep"): self.bus.tkeep.value = 0 self._keep = True
def __init__(self, entity: SimHandleBase, name: str, clock: SimHandleBase, **kwargs: Any): BusDriver.__init__(self, entity, name, clock, **kwargs) # Drive some sensible defaults (setimmediatevalue to avoid x asserts) self.bus.presetn.setimmediatevalue(1) self.bus.penable.setimmediatevalue(0) self.bus.pwrite.setimmediatevalue(0) self.bus.psel.setimmediatevalue(0)
def __init__(self, entity, name, clock, callback=None, **kwargs): # config = kwargs.pop('config', {}) BusDriver.__init__(self, entity, name, clock, **kwargs) self.bus.tvalid.value = 0 self.bus.tdata.value = 0 self.width = len(self.bus.tdata) self._keep = False self._callback = callback if hasattr(self.bus, "tkeep"): self.bus.tkeep.value = 0 self._keep = True
def __init__(self, entity, name, clock, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) # defaults self.bus.tvalid.setimmediatevalue(0) self.bus.tid.setimmediatevalue(0) self.bus.tdest.setimmediatevalue(0) self.bus.tlast.setimmediatevalue(0) self.bus.tkeep.setimmediatevalue(0) self.bus.terr.setimmediatevalue(0) self.bus.tdata.setimmediatevalue(0)
def __init__(self, entity, name, clock, width=32, signals_dict=None, **kwargs): if signals_dict is not None: self._signals = signals_dict BusDriver.__init__(self, entity, name, clock, **kwargs) # Drive some sensible defaults (setimmediatevalue to avoid x asserts) self._width = width self.bus.cyc.setimmediatevalue(0) self.bus.stb.setimmediatevalue(0) self.bus.we.setimmediatevalue(0) self.bus.adr.setimmediatevalue(0) self.bus.datwr.setimmediatevalue(0) if hasattr(self.bus, "sel"): v = self.bus.sel.value v.binstr = "1" * len(self.bus.sel) self.bus.sel.value = v
def __init__(self, entity): BusDriver.__init__(self, entity, "", entity.CLK40) self.hit = BinaryValue(bits=len(self.bus.ANALOG_HIT)) self.hit.value = 0
def __init__(self, entity, name, clock, readlatency_min=1, readlatency_max=1, memory=None, avl_properties={}, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) if avl_properties != {}: for key, value in self._avalon_properties.items(): self._avalon_properties[key] = avl_properties.get(key, value) if self._avalon_properties["burstCountUnits"] != "symbols": self.log.error("Only symbols burstCountUnits is supported") if self._avalon_properties["addressUnits"] != "symbols": self.log.error("Only symbols addressUnits is supported") self._burstread = False self._burstwrite = False self._readable = False self._writeable = False self._width = None if hasattr(self.bus, "readdata"): self._width = len(self.bus.readdata) self.dataByteSize = int(self._width / 8) self._readable = True if hasattr(self.bus, "writedata"): width = len(self.bus.writedata) if (self._width is not None) and self._width != width: self.log.error("readdata and writedata bus" + " are not the same size") self._width = width self.dataByteSize = int(self._width / 8) self._writeable = True if not self._readable and not self._writeable: raise TestError("Attempt to instantiate useless memory") # Allow dual port RAMs by referencing the same dictionary if memory is None: self._mem = {} else: self._mem = memory self._val = BinaryValue(n_bits=self._width, bigEndian=False) self._readlatency_min = readlatency_min self._readlatency_max = readlatency_max self._responses = [] self._coro = cocotb.fork(self._respond()) if hasattr(self.bus, "readdatavalid"): self.bus.readdatavalid.setimmediatevalue(0) if hasattr(self.bus, "waitrequest"): self.bus.waitrequest.setimmediatevalue(0) if hasattr(self.bus, "burstcount"): if hasattr(self.bus, "readdatavalid"): self._burstread = True self._burstwrite = True if self._avalon_properties.get("WriteBurstWaitReq", True): self.bus.waitrequest.value = 1 else: self.bus.waitrequest.value = 0 if hasattr(self.bus, "readdatavalid"): self.bus.readdatavalid.setimmediatevalue(0)
def __init__(self, entity, name, clock, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) self.bus.select.setimmediatevalue(0) self.log.debug("OPBMaster created") self.busy_event = Event("%s_busy" % name) self.busy = False
def __init__(self, entity, name, clock): BusDriver.__init__(self, entity, name, clock) self.clock = clock self.bus.data.setimmediatevalue(0) self.bus.valid.setimmediatevalue(0)
def __init__(self, entity, name, clock, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) self.bus.select.setimmediatevalue(0) self.log.debug("OPBMaster created")
def __init__(self, entity): BusDriver.__init__(self, entity, "", entity.CLK320)
def __init__(self, entity, name, clock, **kwargs): BusDriver.__init__(self, entity, name, clock, **kwargs) self.bus.valid.value = 0