async def dma_io_write(self, addr, data, timeout=0, timeout_unit='ns'):
n = 0
while True:
tlp = Tlp_us()
tlp.fmt_type = TlpType.IO_WRITE
tlp.requester_id = PcieId(0, 0, 0)
first_pad = addr % 4
byte_length = min(len(data) - n, 4 - first_pad)
tlp.set_addr_be_data(addr, data[n:n + byte_length])
tlp.tag = await self.alloc_tag()
await self.rq_source.send(tlp.pack_us_rq())
pkt = await self.rc_sink.recv()
self.release_tag(tlp.tag)
if not pkt:
raise Exception("Timeout")
cpl = Tlp_us.unpack_us_rc(pkt)
if cpl.status != CplStatus.SC:
raise Exception("Unsuccessful completion")
n += byte_length
addr += byte_length
if n >= len(data):
break
async def dma_mem_write(self, addr, data, timeout=0, timeout_unit='ns'):
n = 0
while True:
tlp = Tlp_us()
if addr > 0xffffffff:
tlp.fmt_type = TlpType.MEM_WRITE_64
else:
tlp.fmt_type = TlpType.MEM_WRITE
tlp.requester_id = PcieId(0, 0, 0)
first_pad = addr % 4
byte_length = len(data) - n
# max payload size
byte_length = min(byte_length,
(128 << self.dut.cfg_max_payload.value.integer) -
first_pad)
# 4k address align
byte_length = min(byte_length, 0x1000 - (addr & 0xfff))
tlp.set_addr_be_data(addr, data[n:n + byte_length])
await self.rq_source.send(tlp.pack_us_rq())
n += byte_length
addr += byte_length
if n >= len(data):
break
async def dma_mem_write(self, addr, data, timeout=0, timeout_unit='ns'):
n = 0
while n < len(data):
tlp = Tlp_us()
if addr > 0xffffffff:
tlp.fmt_type = TlpType.MEM_WRITE_64
else:
tlp.fmt_type = TlpType.MEM_WRITE
tlp.requester_id = PcieId(self.dev.bus_num, self.dev.device_num, 0)
first_pad = addr % 4
byte_length = len(data) - n
# max payload size
byte_length = min(byte_length,
(128 << self.dev.functions[0].max_payload_size) -
first_pad)
# 4k address align
byte_length = min(byte_length, 0x1000 - (addr & 0xfff))
tlp.set_addr_be_data(addr, data[n:n + byte_length])
await self.rq_source.send(tlp.pack_us_rq())
n += byte_length
addr += byte_length