def sendByte(self, value, ret=None):
if ret != None:
ret[0] = 0
buffer = [False]
for i in xrange(8):
yield self.sendBit(testBit(value, 7 - i), buffer)
if ret != None:
ret[0] |= buffer[0] << (7 - i)
def sendByte(self, value ,ret = None):
if ret != None :
ret[0] = 0
buffer = [False]
for i in xrange(8):
yield self.sendBit(testBit(value,7-i),buffer)
if ret != None:
ret[0] |= buffer[0] << (7-i)
def exchange(self, masterData):
buffer = ""
if not self.cpha:
for i in range(self.dataWidth):
self.spi.mosi <= testBit(masterData, self.dataWidth - 1 - i)
yield Timer(self.baudPeriode >> 1)
buffer = buffer + str(self.spi.miso.write) if bool(
self.spi.miso.writeEnable) else "x"
self.spi.sclk <= (not self.cpol)
yield Timer(self.baudPeriode >> 1)
self.spi.sclk <= (self.cpol)
else:
for i in range(self.dataWidth):
self.spi.mosi <= testBit(masterData, self.dataWidth - 1 - i)
self.spi.sclk <= (not self.cpol)
yield Timer(self.baudPeriode >> 1)
buffer = buffer + str(self.spi.miso.write) if bool(
self.spi.miso.writeEnable) else "x"
self.spi.sclk <= (self.cpol)
yield Timer(self.baudPeriode >> 1)
raise ReturnValue(buffer)
def spiSlaveAgent(spi, queue, clk):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
@coroutine
def wait(cycles):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
sclkLast = str(spi.sclk)
mosiLast = str(spi.mosi)
ssLast = str(spi.ss)
for i in range(cycles):
yield RisingEdge(clk)
sclkNew = str(spi.sclk)
mosiNew = str(spi.mosi)
ssNew = str(spi.ss)
sclkStable += 1
mosiStable += 1
ssStable += 1
if sclkNew != sclkLast:
sclkStableLast = sclkStable
sclkStable = 0
if mosiNew != mosiLast:
mosiStableLast = mosiStable
mosiStable = 0
if ssNew != ssLast:
ssStableLast = ssStable
ssStable = 0
sclkLast = sclkNew
mosiLast = mosiNew
ssLast = ssNew
ssValue = 0xF
while True:
if queue.empty():
yield wait(1)
# assert(sclkStable > 1)
# assert(mosiStable > 1)
# assert(ssStable > 1)
else:
head = queue.get()
if isinstance(head, SlaveCmdData):
for i in range(8):
if spiConfig.cpha == False:
spi.miso <= testBit(
head.slaveData, 7 -
i) if head.slaveData != None else randBool()
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToggle
assert mosiStable >= spiConfig.sclkToggle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i),
"MOSI mismatch")
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToggle
else:
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
spi.miso <= testBit(
head.slaveData, 7 -
i) if head.slaveData != None else randBool()
assert sclkStableLast >= spiConfig.sclkToggle
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert mosiStable >= spiConfig.sclkToggle
assert sclkStableLast >= spiConfig.sclkToggle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i),
"MOSI mismatch")
elif isinstance(head, SlaveCmdSs):
while True:
yield wait(1)
assert sclkStable > 0
if spi.ss != ssValue:
break
if head.enable:
yield wait(spiConfig.ssSetup - 1)
print(str(ssStable) + " " + str(sclkStable))
assert ssStable >= spiConfig.ssSetup - 1
assert sclkStable >= spiConfig.ssSetup - 1
else:
print(str(ssStableLast) + " " + str(sclkStable))
assert ssStableLast >= spiConfig.ssHold
assert sclkStable >= spiConfig.ssHold
yield wait(spiConfig.ssDisable - 1)
print(str(ssStable) + " " + str(sclkStable))
assert ssStable >= spiConfig.ssDisable - 1
assert sclkStable >= spiConfig.ssDisable - 1
assertEquals(spi.ss,
setBit(ssValue, head.index, not head.enable),
"SS mismatch")
ssValue = int(spi.ss)
def spiSlaveAgent(spi, queue, clk):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
@coroutine
def wait(cycles):
global sclkStable
global mosiStable
global ssStable
global sclkStableLast
global mosiStableLast
global ssStableLast
sclkLast = str(spi.sclk)
mosiLast = str(spi.mosi)
ssLast = str(spi.ss)
for i in xrange(cycles):
yield RisingEdge(clk)
sclkNew = str(spi.sclk)
mosiNew = str(spi.mosi)
ssNew = str(spi.ss)
sclkStable += 1
mosiStable += 1
ssStable += 1
if sclkNew != sclkLast:
sclkStableLast = sclkStable
sclkStable = 0
if mosiNew != mosiLast:
mosiStableLast = mosiStable
mosiStable = 0
if ssNew != ssLast:
ssStableLast = ssStable
ssStable = 0
sclkLast = sclkNew
mosiLast = mosiNew
ssLast = ssNew
ssValue = 0xF
while True:
if queue.empty():
yield wait(1)
# assert(sclkStable > 1)
# assert(mosiStable > 1)
# assert(ssStable > 1)
else:
head = queue.get()
if isinstance(head, SlaveCmdData):
for i in xrange(8):
if spiConfig.cpha == False:
spi.miso <= testBit(head.slaveData, 7-i) if head.slaveData != None else randBool()
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToogle
assert mosiStable >= spiConfig.sclkToogle
assertEquals(spi.mosi, testBit(head.masterData, 7-i),"MOSI missmatch")
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert sclkStableLast >= spiConfig.sclkToogle
else:
while True:
yield wait(1)
if spi.sclk == (not spiConfig.cpol):
break
spi.miso <= testBit(head.slaveData, 7 - i) if head.slaveData != None else randBool()
assert sclkStableLast >= spiConfig.sclkToogle
while True:
yield wait(1)
if spi.sclk == (spiConfig.cpol):
break
assert mosiStable >= spiConfig.sclkToogle
assert sclkStableLast >= spiConfig.sclkToogle
assertEquals(spi.mosi, testBit(head.masterData, 7 - i), "MOSI missmatch")
elif isinstance(head, SlaveCmdSs):
while True:
yield wait(1)
assert sclkStable > 0
if spi.ss != ssValue:
break
if head.enable:
yield wait(spiConfig.ssSetup-1)
print str(ssStable) + " " + str(sclkStable)
assert ssStable >= spiConfig.ssSetup-1
assert sclkStable >= spiConfig.ssSetup-1
else:
print str(ssStableLast) + " " + str(sclkStable)
assert ssStableLast >= spiConfig.ssHold
assert sclkStable >= spiConfig.ssHold
yield wait(spiConfig.ssDisable-1)
print str(ssStable) + " " + str(sclkStable)
assert ssStable >= spiConfig.ssDisable-1
assert sclkStable >= spiConfig.ssDisable-1
assertEquals(spi.ss, setBit(ssValue, head.index, not head.enable), "SS mismatch")
ssValue = int(spi.ss)