def handle_data(self):
"""Process read data."""
if self.write:
# Info row
if self.reg in [Register.MTHIGH, Register.MTLOW]:
ann = AnnInfo.MTREG
val = hlp.format_data(self.mtreg, self.options["radix"])
annots = hlp.compose_annot(info[ann], ann_value=val)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
if self.reg in range(Register.MCHIGH, Register.MOLOW + 1):
ann = AnnInfo.SENSE
val = "{:.2f}".format(self.calculate_sensitivity())
unit = " {}/cnt".format(Params.UNIT_LIGHT)
annots = hlp.compose_annot(info[ann],
ann_value=val,
ann_unit=unit)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
else:
regword = (self.bytes[1] << 8) + self.bytes[0]
# Registers row
ann = AnnRegs.DATA
annots = hlp.compose_annot(registers[ann])
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
# # Info row
ann = AnnInfo.LIGHT
val = "{:.2f}".format(self.calculate_light(regword))
unit = " {}".format(Params.UNIT_LIGHT)
annots = hlp.compose_annot(info[ann], ann_value=val, ann_unit=unit)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
self.clear_data()
def handle_datareg_0x00(self, dataword):
"""Process temperature register."""
temp, unit = self.calculate_temperature(dataword)
# Bits row - EM bit - extended mode
em = int(self.em)
em_l = ("dis", "en")[self.em] + "abled"
em_s = em_l[0].upper()
ann = AnnBits.EM
annots = hlp.compose_annot(bits[ann], [em, em_l, em_s])
self.putd(TempBits.EM, TempBits.EM, [ann, annots])
# Bits row - reserved bits
res_bits = (3, 2)[self.em]
bit_min = TempBits.RESERVED
bit_max = bit_min + res_bits
self.putb(bit_min, bit_max)
# Bits row - data bits
data_bits = 8 * len(self.bytes) - 1 - res_bits
bit_min = bit_max
bit_max = bit_min + data_bits
self.putb(bit_min, bit_max, AnnBits.DATA)
# Registers row
ann = AnnRegs.TEMP
val = hlp.format_data(dataword, self.options["radix"])
annots = hlp.compose_annot(registers[ann], ann_value=val)
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
# Info row
ann = AnnInfo.TEMP
annots = hlp.compose_annot(info[ann], ann_value=temp, ann_unit=unit)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
def check_addr(self, addr_slave):
"""Check correct slave address."""
if addr_slave == Address.SLAVE:
return True
ann = AnnInfo.BADADD
val = hlp.format_data(self.addr, self.options["radix"])
annots = hlp.compose_annot(info[ann], ann_value=val)
self.put(self.ss, self.es, self.out_ann, [ann, annots])
return False
def handle_pointer(self):
"""Process register pointer."""
# Registers row
ann = AnnRegs.POINTER
val = hlp.format_data(self.reg, self.options["radix"])
act = self.format_rw()
annots = hlp.compose_annot(registers[ann],
ann_value=val,
ann_action=act)
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
self.clear_data()
def handle_reg_0x3f(self, databyte):
"""Process NVRAM."""
# Bits row
ann = AnnBits.NVRAM
val = hlp.format_data(databyte, self.options["radix"])
annots = hlp.compose_annot(bits[ann], ann_value=val)
self.putd(0, 7, [ann, annots])
# Registers row
ann = AnnRegs.NVRAM
act = self.format_rw()
annots = hlp.compose_annot(registers[ann], ann_action=act)
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
def check_addr(self, addr_slave, check_gencall=False):
"""Check correct slave address or general call."""
if addr_slave in (
Address.GND,
Address.VCC,
Address.SDA,
Address.SCL,
) or not check_gencall or addr_slave == GeneralCall.ADDRESS:
return True
ann = AnnInfo.BADADD
val = hlp.format_data(self.addr, self.options["radix"])
annots = hlp.compose_annot(info[ann], ann_value=val)
self.put(self.ss, self.es, self.out_ann, [ann, annots])
return False
def handle_datareg_0x03(self, dataword):
"""Process THIGH register."""
temp, unit = self.calculate_temperature(dataword)
# Registers row
ann = AnnRegs.THIGH
val = hlp.format_data(dataword, self.options["radix"])
annots = hlp.compose_annot(registers[ann], ann_value=val)
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
# Info row
ann = AnnInfo.THIGH
act = self.format_rw()
annots = hlp.compose_annot(info[ann],
ann_value=temp,
ann_unit=unit,
ann_action=act)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
def handle_datareg_0x01(self, dataword):
"""Process configuration register."""
# Bits row - OS bit - one-shot measurement
os = dataword >> ConfigBits.OS & 1
os_l = ("dis", "en")[os] + "abled"
os_s = os_l[0].upper()
ann = AnnBits.OS
annots = hlp.compose_annot(bits[ann], [os, os_l, os_s])
self.putd(ConfigBits.OS, ConfigBits.OS, [ann, annots])
# Bits row - R0/R1 bits - converter resolution
res = resolutions[dataword >> ConfigBits.R0 & 0b11]
ann = AnnBits.R0
val = "{}".format(res)
annots = hlp.compose_annot(bits[ann], ann_value=val, ann_unit="bit")
self.putd(ConfigBits.R0, ConfigBits.R1, [ann, annots])
# Bits row - F0/F1 bits - fault queue
flt = faults[dataword >> ConfigBits.F0 & 0b11]
ann = AnnBits.F0
val = "{}".format(flt)
annots = hlp.compose_annot(bits[ann], ann_value=val)
self.putd(ConfigBits.F0, ConfigBits.F1, [ann, annots])
# Bits row - POL bit - polarity, alert active
pol = dataword >> ConfigBits.POL & 1
pol_l = ("low", "high")[pol]
pol_s = pol_l[0].upper()
ann = AnnBits.POL
annots = hlp.compose_annot(bits[ann], ann_value=[pol, pol_l, pol_s])
self.putd(ConfigBits.POL, ConfigBits.POL, [ann, annots])
# Bits row - TM bit - thermostat mode
tm = dataword >> ConfigBits.TM & 1
tm_l = ("comparator", "interrupt")[tm]
tm_s = tm_l[0].upper()
ann = AnnBits.TM
annots = hlp.compose_annot(bits[ann], ann_value=[tm, tm_l, tm_s])
self.putd(ConfigBits.TM, ConfigBits.TM, [ann, annots])
# Bits row - SD bit - shutdown mode
sd = dataword >> ConfigBits.SD & 1
sd_l = ("dis", "en")[sd] + "abled"
sd_s = sd_l[0].upper()
ann = AnnBits.SD
annots = hlp.compose_annot(bits[ann], ann_value=[sd, sd_l, sd_s])
self.putd(ConfigBits.SD, ConfigBits.SD, [ann, annots])
# Bits row - CR0/CR1 bits - conversion rate
rate = rates[dataword >> ConfigBits.CR0 & 0b11]
ann = AnnBits.CR0
annots = hlp.compose_annot(bits[ann], ann_value=rate, ann_unit="Hz")
self.putd(ConfigBits.CR0, ConfigBits.CR1, [ann, annots])
# Bits row - AL bit - alert
al = dataword >> ConfigBits.AL & 1
al_l = ("", "in")[al ^ pol] + "active"
al_s = al_l[0].upper()
ann = AnnBits.AL
annots = hlp.compose_annot(bits[ann], ann_value=[al, al_l, al_s])
self.putd(ConfigBits.AL, ConfigBits.AL, [ann, annots])
# Bits row - EM bit - extended mode
em = dataword >> ConfigBits.EM & 1
self.em = bool(em)
em_l = ("dis", "en")[em] + "abled"
em_s = em_l[0].upper()
ann = AnnBits.EM
annots = hlp.compose_annot(bits[ann], ann_value=[em, em_l, em_s])
self.putd(ConfigBits.EM, ConfigBits.EM, [ann, annots])
# Bits row - reserved bits
for i in range(ConfigBits.EM - 1, -1, -1):
self.putb(i)
# Registers row
ann = AnnRegs.CONF
val = hlp.format_data(dataword, self.options["radix"])
annots = hlp.compose_annot(registers[ann], ann_value=val)
self.put(self.ssd, self.es, self.out_ann, [ann, annots])
# Info row
ann = AnnInfo.CONF
val = info[prm_annots[(Params.CUSTOM,
dataword)[dataword == Params.POWERUP]]]
act = self.format_rw()
annots = hlp.compose_annot(info[ann], ann_value=val, ann_action=act)
self.put(self.ssb, self.es, self.out_ann, [ann, annots])
