def main():
parser = argparse.ArgumentParser(epilog=__doc__)
HMC.add_options(parser)
parser.add_argument("commands_to_run",
metavar="command(s)",
nargs='*',
help="Command(s) to run")
parser.add_argument("--cpu",
type=str,
choices=cpu_types.keys(),
default="atomic",
help="CPU model to use")
parser.add_argument("--cpu-freq", type=str, default="4GHz")
parser.add_argument("--num-cores",
type=int,
default=1,
help="Number of CPU cores")
# parser.add_argument("--mem-type", default="DDR3_1600_8x8",
# choices=MemConfig.mem_names(),
# help = "type of memory to use")
# parser.add_argument("--mem-channels", type=int, default=2,
# help = "number of memory channels")
# parser.add_argument("--mem-ranks", type=int, default=None,
# help = "number of memory ranks per channel")
parser.add_argument("--mem-size",
action="store",
type=str,
default="2GB",
help="Specify the physical memory size")
args = parser.parse_args()
# Create a single root node for gem5's object hierarchy. There can
# only exist one root node in the simulator at any given
# time. Tell gem5 that we want to use syscall emulation mode
# instead of full system mode.
root = Root(full_system=False)
# Populate the root node with a system. A system corresponds to a
# single node with shared memory.
root.system = create(args)
# Instantiate the C++ object hierarchy. After this point,
# SimObjects can't be instantiated anymore.
m5.instantiate()
# Start the simulator. This gives control to the C++ world and
# starts the simulator. The returned event tells the simulation
# script why the simulator exited.
event = m5.simulate()
# Print the reason for the simulation exit. Some exit codes are
# requests for service (e.g., checkpoints) from the simulation
# script. We'll just ignore them here and exit.
print(event.getCause(), " @ ", m5.curTick())
sys.exit(event.getCode())
def main():
parser = argparse.ArgumentParser(description="Simple system using HMC as\
main memory")
HMC.add_options(parser)
add_options(parser)
options = parser.parse_args()
# build the system
root = build_system(options)
# instantiate all of the objects we've created so far
m5.instantiate()
print("Beginning simulation!")
event = m5.simulate(10000000000)
m5.stats.dump()
print('Exiting @ tick %i because %s (exit code is %i)' %
(m5.curTick(), event.getCause(), event.getCode()))
print("Done")
def main():
parser = argparse.ArgumentParser(description="Simple system using HMC as\
main memory")
HMC.add_options(parser)
add_options(parser)
options = parser.parse_args()
# build the system
root = build_system(options)
# instantiate all of the objects we've created so far
m5.instantiate()
print("Beginning simulation!")
event = m5.simulate(10000000000)
m5.stats.dump()
print('Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(),
event.getCause(),
event.getCode()))
print("Done")
# Author: Éder F. Zulian
import sys
import argparse
import m5
from m5.objects import *
from m5.util import *
addToPath('../')
from common import MemConfig
from common import HMC
pd = "Simple 'hello world' example using HMC as main memory"
parser = argparse.ArgumentParser(description=pd)
HMC.add_options(parser)
options = parser.parse_args()
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '1GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# create a simple CPU
system.cpu = TimingSimpleCPU()
# config memory system
MemConfig.config_mem(options, system)
# hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave
# Author: Éder F. Zulian
import sys
import argparse
import m5
from m5.objects import *
from m5.util import *
addToPath('../')
from common import MemConfig
from common import HMC
pd = "Simple 'hello world' example using HMC as main memory"
parser = argparse.ArgumentParser(description=pd)
HMC.add_options(parser)
options = parser.parse_args()
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '1GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# create a simple CPU
system.cpu = TimingSimpleCPU()
# config memory system
MemConfig.config_mem(options, system)
# hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave