def api(self, command, data):
if command == 'echo':
return data
elif command == 'clear_cache':
cache.clear_cache(data['project_id'])
return {}
elif command == 'compile':
project_id = data['project_id']
sources = data['sources']
components = [
ComponentSpec(c['name'], c['ports'])
for c in data['components']
]
compile.start_compilation(project_id, sources, components)
return {}
elif command == 'build_progress':
project_id = data['project_id']
logs = []
is_running = project_id in compile.running_threads
last_completed = cache.get_overlay_modified_date(project_id)
# logs
if project_id in compile.running_logs:
while not compile.running_logs[project_id].empty():
logs.append(compile.running_logs[project_id].get_nowait())
progress = compile.running_logs[project_id].progress
else:
if last_completed != 0:
progress = 100
else:
progress = 0
# report
if is_running:
last_build_status = ''
build_report = ''
source_mappings = []
else:
last_build_status, build_report = cache.get_build_report(
project_id)
source_mappings = cache.get_source_mapping(project_id)
return {
"running": is_running,
"progress": progress,
"last_completed": last_completed,
"last_build_status": last_build_status,
"build_report": build_report,
"source_mappings": source_mappings,
"logs": ''.join(logs)
}
elif command == 'cancel_build':
project_id = data['project_id']
compile.cancel_compilation(project_id)
return {}
elif command == 'download_overlay_bit':
project_id = data['project_id']
return {"file": cache.get_overlay_bit_path(project_id)}
elif command == 'download_overlay_tcl':
project_id = data['project_id']
return {"file": cache.get_overlay_tcl_path(project_id)}
elif command == 'download_python_api':
project_id = data['project_id']
return {"file": cache.get_python_api_path(project_id)}
else:
return self._error('Command not supported')
def test_outputs(self):
c = ComponentSpec("myname", [{"name": "o", "type": "output"}])
a = _build_component_list([c])
self.assertEqual(len(a), 1)
self.assertEqual(a[0], "myname = Component(_overlay.myname_0, {}, {\"o\": 4})")
def test_empty(self):
c = ComponentSpec("myname", [])
a = _build_component_list([c])
self.assertEqual(len(a), 1)
self.assertEqual(a[0], "myname = Component(_overlay.myname_0, {}, {})")
def test_name(self):
c = ComponentSpec("myname", [])
a = template_args(c)
self.assertEqual(a["component_name"], "myname")
def test_axi_width3(self):
c = ComponentSpec("name", [
{"name": f"p{i}", "type": "input"} for i in range(10)
])
a = template_args(c)
self.assertEqual(a["axi_address_width"], 6)
def create_wrapper(component_spec: ComponentSpec, verilog_sources):
log_count = math.ceil(math.log2(max(4, component_spec.register_count())))
axi_address_width = log_count + 2
internal_address_width = log_count - 1
internal_wire_declarations = [f"wire [31:0] {p};" for p in component_spec.output_ports()]
slave_register_declarations = [f"reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg{i};"
for i
in range(component_spec.register_count())]
slave_axi_resets = [f"slv_reg{i} <= 0;"
for i
in range(component_spec.register_count())]
write_enable_cases = []
for i in range(component_spec.register_count()):
write_enable_cases.append("""
%d:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
slv_reg%d[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
""" % (i, i))
write_enable_cases.append('default : begin')
for i in range(component_spec.register_count()):
write_enable_cases.append(f"slv_reg{i} <= slv_reg{i};")
write_enable_cases.append('end')
reg_out_cases = ["0 : reg_data_out <= sygnaller_scope;"]
for i in range(1, component_spec.register_count()):
if component_spec.is_output(i - 1):
reg_out_cases.append(f"{i} : reg_data_out <= module_output{i};")
else:
reg_out_cases.append(f"{i} : reg_data_out <= slv_reg{i};")
user_logic_args = []
for i, p in enumerate(component_spec.port_list):
if p.port_type == 'clock':
user_logic_args.append('S_AXI_ACLK')
elif p.port_type == 'input':
user_logic_args.append(f'slv_reg{i+1}')
elif p.port_type == 'output':
user_logic_args.append(f'module_output{i+1}')
elif p.port_type == 'video in':
user_logic_args.append(f'video_in')
elif p.port_type == 'video ready':
user_logic_args.append(f'video_in_ready')
elif p.port_type == 'video x':
user_logic_args.append(f'video_x')
elif p.port_type == 'video y':
user_logic_args.append(f'video_y')
elif p.port_type == 'video out':
user_logic_args.append(f'video_out')
elif p.port_type == 'scope':
user_logic_args.append(f'sygnaller_scope')
user_logic = component_spec.name + ' module_instance(' + ', '.join(user_logic_args) + ');'
if not component_spec.has_scope_port():
user_logic += "\n" + "assign sygnaller_scope = 0;"
args = {
"component_name": component_spec.name,
"verilog_source": '\n'.join(verilog_sources),
"axi_address_width": axi_address_width,
"internal_address_width": internal_address_width,
"internal_wire_declarations": '\n'.join(internal_wire_declarations),
"slave_register_declaration": '\n'.join(slave_register_declarations),
"slave_axi_resets": '\n'.join(slave_axi_resets),
"write_enable_cases": '\n'.join(write_enable_cases),
"reg_out_cases": '\n'.join(reg_out_cases),
"user_logic": user_logic
}
return template(args)