def test_threeinputnand():
nand = ThreeInputNand()
p_a = Power()
p_b = Power()
p_c = Power()
p_a.connect(nand.input_a)
p_b.connect(nand.input_b)
p_c.connect(nand.input_c)
assert nand.output.value
p_a.on()
assert nand.output.value
p_b.on()
assert nand.output.value
p_c.on()
assert not nand.output.value
p_a.off()
assert nand.output.value
def test_twotofourdecoder():
dc = TwoToFourDecoder()
_str = dc.__str__()
in1 = Power()
in2 = Power()
in1.connect(dc.input_a)
in2.connect(dc.input_b)
assert dc.output_a.value
assert not dc.output_b.value
assert not dc.output_c.value
assert not dc.output_d.value
in1.on()
assert not dc.output_a.value
assert dc.output_b.value
assert not dc.output_c.value
assert not dc.output_d.value
in1.off()
in2.on()
assert not dc.output_a.value
assert not dc.output_b.value
assert dc.output_c.value
assert not dc.output_d.value
in1.on()
in2.on()
assert not dc.output_a.value
assert not dc.output_b.value
assert not dc.output_c.value
assert dc.output_d.value
def test_power():
p = Power()
assert not p.value
p.on()
assert p.value
p.off()
assert not p.value
p = Power(on=True)
assert p.value
def test_eightbitripplecounter():
rc = EightBitRippleCounter()
clk = Power()
print(rc)
clk.connect(rc.clock)
clk.on()
print(rc)
clk.off()
print(rc)
clk.on()
print(rc)
def test_alu():
alu = ALU()
_str = alu.__str__()
#create input power switches and connect up ripple carry adder
inputs_a = get_eight_bit_switch(alu.input_a)
inputs_b = get_eight_bit_switch(alu.input_b)
op = Power()
op.connect(alu.operator)
#do some random tests
no_tests = 100
for i in range(no_tests):
#turn on random bits
for in_bit in inputs_a:
in_bit.off()
if randint(0, 2) == 2:
in_bit.on()
for in_bit in inputs_b:
in_bit.off()
if randint(0, 2) == 2:
in_bit.on()
#random op
op.off()
if randint(0, 1) == 1:
op.on()
#subtract
if op.value:
#if no overflow did it calculate correctly
if alu.carry.value:
assert alu.input_a.int_value - alu.input_b.int_value == alu.sum.int_value
assert not alu.overflow.value
assert not alu.negative.value
#was there an overflow? if so was the result less than 0
if not alu.carry.value:
assert alu.input_a.int_value - alu.input_b.int_value < 0
assert alu.overflow.value
assert alu.negative.value
#addition
else:
#was there an overflow? if so was the result over 255
if alu.carry.value:
assert alu.input_a.int_value + alu.input_b.int_value > 255
assert alu.overflow.value
assert not alu.negative.value
#if no overflow did it calculate correctly
if not alu.carry.value:
assert alu.input_a.int_value + alu.input_b.int_value == alu.sum.int_value
assert not alu.overflow.value
assert not alu.negative.value
def test_halfadder():
ha = HalfAdder()
_str = ha.__str__()
in1 = Power()
in2 = Power()
in1.connect(ha.input_a)
in2.connect(ha.input_b)
in1.off()
in2.off()
assert not ha.sum.value
assert not ha.carry.value
in1.on()
in2.off()
assert ha.sum.value
assert not ha.carry.value
in1.off()
in2.on()
assert ha.sum.value
assert not ha.carry.value
in1.on()
in2.on()
assert not ha.sum.value
assert ha.carry.value
def test_transistor():
t = Transistor(connect_to_power=False)
p = Power()
sw = Power()
p.connect(t.collector)
sw.connect(t.base)
p.off()
sw.off()
assert not t.collector.value
assert not t.collector_output.value
assert not t.base.value
assert not t.emitter.value
p.on()
assert t.collector.value
assert t.collector_output.value
assert not t.base.value
assert not t.emitter.value
sw.on()
assert t.collector.value
assert not t.collector_output.value
assert t.base.value
assert t.emitter.value
sw.off()
assert t.collector.value
assert t.collector_output.value
assert not t.base.value
assert not t.emitter.value
p.off()
assert not t.collector.value
assert not t.collector_output.value
assert not t.base.value
assert not t.emitter.value
def test_eightbitripplecarryaddersubtractor():
rcas = EightBitRippleCarryAdderSubtractor()
_str = rcas.__str__()
#create input power switches and connect up ripple carry adder
inputs_a = get_eight_bit_switch(rcas.input_a)
inputs_b = get_eight_bit_switch(rcas.input_b)
op = Power()
op.connect(rcas.operator)
#do some random tests
no_tests = 100
for i in range(no_tests):
#turn on random bits
for in_bit in inputs_a:
in_bit.off()
if randint(0, 2) == 2:
in_bit.on()
for in_bit in inputs_b:
in_bit.off()
if randint(0, 2) == 2:
in_bit.on()
#random op
op.off()
if randint(0, 1) == 1:
op.on()
#subtract
if op.value:
#if no overflow did it calculate correctly
if rcas.carry.value:
assert rcas.input_a.int_value - rcas.input_b.int_value == rcas.sum.int_value
#was there an overflow? if so was the result less than 0
if not rcas.carry.value:
assert rcas.input_a.int_value - rcas.input_b.int_value < 0
#addition
else:
#was there an overflow? if so was the result over 255
if rcas.carry.value:
assert rcas.input_a.int_value + rcas.input_b.int_value > 255
#if no overflow did it calculate correctly
if not rcas.carry.value:
assert rcas.input_a.int_value + rcas.input_b.int_value == rcas.sum.int_value
def test_eightbitregister():
reg = EightBitRegister()
_str = reg.__str__()
#create input power switches and connect up the register
inputs_data = []
for i in range(8):
input_bit = Power()
input_bit.connect(reg.data.get_bit(i))
inputs_data.append(input_bit)
input_write = Power()
input_write.connect(reg.write)
#initial output should be 0
last_write_value = 0
assert reg.output.int_value == last_write_value
#do some random tests
no_tests = 100
for i in range(no_tests):
#turn on random bits
for input_data in inputs_data:
if getrandbits(1) == 1:
input_data.on()
else:
input_data.off()
#write hasnt been enabled the output shouldnt have changed
assert reg.output.int_value == last_write_value
#randomly turn on write enable
if getrandbits(1) == 1:
input_write.on()
#if it was write enabled update the last write value
last_write_value = reg.data.int_value
else:
input_write.off()
#test to see if the output is still correct
assert reg.output.int_value == last_write_value
input_write.off()
def test_fourtoonemultiplexer():
mp = FourToOneMultiplexer()
_str = mp.__str__()
in1 = Power()
in2 = Power()
in3 = Power()
in4 = Power()
sig1 = Power()
sig2 = Power()
in1.connect(mp.input_a)
in2.connect(mp.input_b)
in3.connect(mp.input_c)
in4.connect(mp.input_d)
sig1.connect(mp.signal_a)
sig2.connect(mp.signal_b)
assert not mp.output.value
in1.on()
assert mp.output.value
sig1.on()
assert not mp.output.value
in2.on()
assert mp.output.value
sig2.on()
assert not mp.output.value
in4.on()
assert mp.output.value
sig1.off()
assert not mp.output.value
in3.on()
assert mp.output.value
in3.off()
assert not mp.output.value
def test_dflipflop():
p_d = Power()
p_clk = Power()
d = DFlipFlop()
p_d.connect(d.input_d)
p_clk.connect(d.clock)
#clock is off, d is off
assert not d.output_q.value
assert d.output_q_.value
p_clk.on()
assert d.output_q.value
assert not d.output_q_.value
#turn d on, it should flip
p_d.on()
assert not d.output_q.value
assert d.output_q_.value
#turn d off, it should flip
p_d.off()
assert d.output_q.value
assert not d.output_q_.value
#turn d on, it should flip
p_d.on()
assert not d.output_q.value
assert d.output_q_.value
#turn clock off
p_clk.off()
assert not d.output_q.value
assert d.output_q_.value
#turning d on should do nothing
p_d.on()
assert not d.output_q.value
assert d.output_q_.value
def test_twotoonemultiplexer():
mp = TwoToOneMultiplexer()
_str = mp.__str__()
in1 = Power()
in2 = Power()
sig = Power()
in1.connect(mp.input_a)
in2.connect(mp.input_b)
sig.connect(mp.signal)
#when the signal is off, output is a, when signal is on output is b
assert not mp.output.value
in1.on()
assert mp.output.value
sig.on()
assert not mp.output.value
in2.on()
assert mp.output.value
sig.off()
assert mp.output.value
in1.off()
assert not mp.output.value
sig.on()
assert mp.output.value
in2.off()
assert not mp.output.value
def test_split():
sw = Power()
c1 = Cathode()
c2 = Cathode()
c3 = Cathode()
split = Split(c1, c2)
sw.connect(split.input)
sw.off()
assert not split.input.value
assert not c1.value
assert not c2.value
sw.on()
assert split.input.value
assert c1.value
assert c2.value
split.connect(c3)
assert c3.value
sw.off()
assert not split.input.value
assert not c1.value
assert not c2.value
assert not c3.value
def test_srflipflop():
p_set = Power()
p_reset = Power()
sr = SRFlipFlop()
p_set.connect(sr.set)
p_reset.connect(sr.reset)
assert sr.output_q_.value
assert not sr.output_q.value
p_set.on()
assert not sr.output_q_.value
assert sr.output_q.value
p_set.off()
assert not sr.output_q_.value
assert sr.output_q.value
p_reset.on()
assert sr.output_q_.value
assert not sr.output_q.value
p_reset.off()
assert sr.output_q_.value
assert not sr.output_q.value
#might as well test the 'illegal' state
p_set.on()
p_reset.on()
assert not sr.output_q_.value
assert not sr.output_q.value
def test_jkflipflop():
p_j = Power()
p_k = Power()
p_clk = Power()
jk = JKFlipFlop()
p_j.connect(jk.input_j)
p_k.connect(jk.input_k)
p_clk.connect(jk.clock)
assert jk.output_q_.value
assert not jk.output_q.value
p_j.on()
assert jk.output_q_.value
assert not jk.output_q.value
p_clk.on()
assert not jk.output_q_.value
assert jk.output_q.value
p_j.off()
assert not jk.output_q_.value
assert jk.output_q.value
p_clk.off()
assert not jk.output_q_.value
assert jk.output_q.value
p_k.on()
assert not jk.output_q_.value
assert jk.output_q.value
p_clk.on()
assert jk.output_q_.value
assert not jk.output_q.value
p_k.off()
assert jk.output_q_.value
assert not jk.output_q.value
p_clk.off()
assert jk.output_q_.value
assert not jk.output_q.value
def test_andorlatch():
latch = AndOrLatch()
_str = latch.__str__()
input_set = Power()
input_reset = Power()
input_set.connect(latch.set)
input_reset.connect(latch.reset)
assert not latch.set.value
assert not latch.reset.value
assert not latch.output.value
input_set.on()
assert latch.set.value
assert not latch.reset.value
assert latch.output.value
input_set.off()
assert not latch.set.value
assert not latch.reset.value
assert latch.output.value
input_reset.on()
assert not latch.set.value
assert latch.reset.value
assert not latch.output.value
input_set.on()
assert latch.set.value
assert latch.reset.value
assert not latch.output.value
input_reset.off()
assert latch.set.value
assert not latch.reset.value
assert latch.output.value
input_set.off()
assert not latch.set.value
assert not latch.reset.value
assert latch.output.value
def test_gatedlatch():
latch = GatedLatch()
_str = latch.__str__()
input_data = Power()
input_write = Power()
input_data.connect(latch.data)
input_write.connect(latch.write)
assert not latch.data.value
assert not latch.write.value
assert not latch.output.value
input_data.on()
assert latch.data.value
assert not latch.write.value
assert not latch.output.value
input_write.on()
assert latch.data.value
assert latch.write.value
assert latch.output.value
input_write.off()
assert latch.data.value
assert not latch.write.value
assert latch.output.value
input_data.off()
assert not latch.data.value
assert not latch.write.value
assert latch.output.value
input_write.on()
assert not latch.data.value
assert latch.write.value
assert not latch.output.value
input_write.off()
assert not latch.data.value
assert not latch.write.value
assert not latch.output.value
def test_join():
sw1 = Power()
sw2 = Power()
sw3 = Power()
o = Cathode()
j = Join(sw1, sw2)
j.output.connect(o)
sw1.off()
sw2.off()
sw3.off()
assert not j.value
assert not o.value
sw1.on()
assert j.value
assert o.value
sw2.on()
assert j.value
assert o.value
sw1.off()
sw2.off()
assert not j.value
assert not o.value
sw3.on()
j.connect(sw3)
assert j.value
assert o.value
sw1.off()
sw2.off()
sw3.off()
assert not j.value
assert not o.value
def test_fulladder():
fa = FullAdder()
_str = fa.__str__()
in1 = Power()
in2 = Power()
in3 = Power()
in1.connect(fa.input_a)
in2.connect(fa.input_b)
in3.connect(fa.input_c)
in1.off()
in2.off()
in3.off()
assert not fa.carry.value
assert not fa.sum.value
in1.on()
in2.off()
in3.off()
assert not fa.carry.value
assert fa.sum.value
in1.off()
in2.off()
in3.on()
assert not fa.carry.value
assert fa.sum.value
in1.off()
in2.on()
in3.off()
assert not fa.carry.value
assert fa.sum.value
in1.on()
in2.on()
in3.off()
assert fa.carry.value
assert not fa.sum.value
in1.off()
in2.on()
in3.on()
assert fa.carry.value
assert not fa.sum.value
in1.on()
in2.off()
in3.on()
assert fa.carry.value
assert not fa.sum.value
in1.on()
in2.on()
in3.on()
assert fa.carry.value
assert fa.sum.value
def test_msjkflipflop():
p_j = Power()
p_k = Power()
p_clk = Power()
msjk = MasterSlaveJKFlipFlop()
p_j.connect(msjk.input_j)
p_k.connect(msjk.input_k)
p_clk.connect(msjk.clock)
assert msjk.output_q.value
assert not msjk.output_q_.value
# RESET
p_clk.on()
p_k.on()
# it should reset until the clock goes low
assert msjk.output_q.value
# did it reset
p_clk.off()
assert not msjk.output_q.value
assert msjk.output_q_.value
# make sure the value doesnt change when reset is turned off
p_k.off()
assert not msjk.output_q.value
assert msjk.output_q_.value
# or when the clock is back on
p_clk.on()
assert not msjk.output_q.value
assert msjk.output_q_.value
# SET
p_j.on()
# it shouldnt set until the clock goes low
assert not msjk.output_q.value
assert msjk.output_q_.value
# did it set
p_clk.off()
assert msjk.output_q.value
assert not msjk.output_q_.value
# make sure the value doesnt change when set is turned off
p_j.off()
assert msjk.output_q.value
assert not msjk.output_q_.value
# or when the clock is back on
p_clk.on()
assert msjk.output_q.value
assert not msjk.output_q_.value
# RESET
p_k.on()
p_clk.off()
assert not msjk.output_q.value
assert msjk.output_q_.value
def test_sixteenbytememory():
mem = SixteenByteMemory()
# create input power switches and connect up
inputs_address = []
for i in range(4):
input_bit = Power()
input_bit.connect(mem.address.get_bit(i))
inputs_address.append(input_bit)
inputs_data = get_eight_bit_switch(mem.data_in)
input_write = Power()
input_write.connect(mem.write_enable)
input_read = Power()
input_read.connect(mem.read_enable)
# test that you can only read and write when enabled
# test - its not written
inputs_data[0].on()
assert mem.data_out.int_value == 0
# write a value
input_write.on()
input_write.off()
# test - its not being read
assert mem.data_out.int_value == 0
# test - that it can be read
input_read.on()
assert mem.data_out.int_value == 1
input_read.off()
inputs_data[0].off()
# get all possible addresses
addresses = get_binary_states(4)
# write random values to memory addresses
test_values = []
for address in addresses:
inputs_address[0].value = address[0]
inputs_address[1].value = address[1]
inputs_address[2].value = address[2]
inputs_address[3].value = address[3]
# create a random 8 bit value
input_write.on()
test_value = []
for i in range(8):
bit = bool(getrandbits(1))
inputs_data[i].value = bit
test_value.append(bit)
input_write.off()
test_values.append(test_value)
#read values from memory and check they match
a = 0
for address in addresses:
inputs_address[0].value = address[0]
inputs_address[1].value = address[1]
inputs_address[2].value = address[2]
inputs_address[3].value = address[3]
input_read.on()
for i in range(8):
assert mem.data_out.bits[i].value == test_values[a][i]
input_read.off()
a += 1
def test_sixteenbitmemory():
mem = SixteenBitMemory()
_str = mem.__str__()
# create input power switches and connect up
inputs_address = []
for i in range(4):
input_bit = Power()
input_bit.connect(mem.address.get_bit(i))
inputs_address.append(input_bit)
input_data = Power()
input_data.connect(mem.data_in)
input_write = Power()
input_write.connect(mem.write_enable)
input_read = Power()
input_read.connect(mem.read_enable)
# test that you can only read and write when enabled
# test - its not written
input_data.on()
assert not mem.data_out.value
# write a value
input_write.on()
input_write.off()
# test - its not being read
assert not mem.data_out.value
# test - that it can be read
input_read.on()
assert mem.data_out.value
input_read.off()
input_data.off()
# get all possible addresses
addresses = get_binary_states(4)
#write random values to memory addresses
test_values = []
for address in addresses:
inputs_address[0].value = address[0]
inputs_address[1].value = address[1]
inputs_address[2].value = address[2]
inputs_address[3].value = address[3]
test_value = bool(getrandbits(1))
input_write.on()
input_data.value = test_value
input_write.off()
test_values.append(test_value)
input_data.off()
#read values from memory and check they match
a = 0
for address in addresses:
inputs_address[0].value = address[0]
inputs_address[1].value = address[1]
inputs_address[2].value = address[2]
inputs_address[3].value = address[3]
input_read.on()
assert mem.data_out.value == test_values[a]
input_read.off()
a += 1
def test_ramcell():
rc = RAMCell()
_str = rc.__str__()
in_col = Power()
in_row = Power()
in_we = Power()
in_re = Power()
in_data = Power()
in_col.connect(rc.col)
in_row.connect(rc.row)
in_we.connect(rc.write_enable)
in_re.connect(rc.read_enable)
in_data.connect(rc.data_in)
assert not rc.col.value
assert not rc.row.value
assert not rc.write_enable.value
assert not rc.read_enable.value
assert not rc.data_in.value
assert not rc.data_out.value
#data can only be written if the col, row are on
in_we.on()
in_data.on()
assert not rc.col.value
assert not rc.row.value
assert rc.write_enable.value
assert not rc.read_enable.value
assert rc.data_in.value
assert not rc.data_out.value
in_we.off()
in_re.on()
assert not rc.col.value
assert not rc.row.value
assert not rc.write_enable.value
assert rc.read_enable.value
assert rc.data_in.value
assert not rc.data_out.value
in_re.off()
in_data.off()
assert not rc.col.value
assert not rc.row.value
assert not rc.write_enable.value
assert not rc.read_enable.value
assert not rc.data_in.value
assert not rc.data_out.value
#write data to 1
in_col.on()
in_row.on()
in_we.on()
in_data.on()
assert rc.col.value
assert rc.row.value
assert rc.write_enable.value
assert not rc.read_enable.value
assert rc.data_in.value
assert not rc.data_out.value
#read data
in_we.off()
in_data.off()
in_re.on()
assert rc.col.value
assert rc.row.value
assert not rc.write_enable.value
assert rc.read_enable.value
assert not rc.data_in.value
assert rc.data_out.value
in_re.off()
#write data to 0
in_we.on()
in_data.off()
assert rc.col.value
assert rc.row.value
assert rc.write_enable.value
assert not rc.read_enable.value
assert not rc.data_in.value
assert not rc.data_out.value
#read data
in_we.off()
in_data.off()
in_re.on()
assert rc.col.value
assert rc.row.value
assert not rc.write_enable.value
assert rc.read_enable.value
assert not rc.data_in.value
assert not rc.data_out.value
#turn it all off
in_re.off()
in_col.off()
in_row.off()
assert not rc.col.value
assert not rc.row.value
assert not rc.write_enable.value
assert not rc.read_enable.value
assert not rc.data_in.value
assert not rc.data_out.value