def simulate(): # don't make the simulation take all day global SECOND, DELTA_PHASE SECOND = 200 DELTA_PHASE = compute_delta_phase(1000) fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit = make_fpga_ios() @instance def bench(): fastclk.next = 0 reset.next = 0 param_data.next = 0 param_clk.next = 0 audio_req.next = 0 audio_ack.next = 0 yield delay(1) reset.next = 1 yield delay(1) reset.next = 0 # for i in range(8 * SECOND * 32000000 / 40000): for i in range(SECOND * 32000000 / 40000): yield delay(1) fastclk.next = 1 yield delay(1) fastclk.next = 0 stuff = [ bench, fpga(fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit) ] return stuff
def simulate(): # don't make the simulation take all day global SECOND, DELTA_PHASE SECOND = 200 DELTA_PHASE = compute_delta_phase(1000) fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit = make_fpga_ios( ) @instance def bench(): fastclk.next = 0 reset.next = 0 param_data.next = 0 param_clk.next = 0 audio_req.next = 0 audio_ack.next = 0 yield delay(1) reset.next = 1 yield delay(1) reset.next = 0 # for i in range(8 * SECOND * 32000000 / 40000): for i in range(SECOND * 32000000 / 40000): yield delay(1) fastclk.next = 1 yield delay(1) fastclk.next = 0 stuff = [ bench, fpga(fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit) ] return stuff
AUDIO_RATE, DIVIDER, N, WHOLE, HALF, MASK, SECOND, compute_delta_phase, unsigned_bus, signed_bus, signed_to_unsigned, unsigned_to_signed ) A_ABOVE_MIDDLE_C = compute_delta_phase(440) DELTA_PHASE = A_ABOVE_MIDDLE_C def make_fpga_ios(): fastclk = Signal(False) reset = Signal(False) param_data = unsigned_bus(4) param_clk = Signal(False) audio_req = Signal(False) audio_ack = Signal(False) dac_bit = Signal(True) return (fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit) def fpga(fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit):
import unittest import sys from myhdl import Signal, delay, Simulation, always_comb, \ instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals from wavegen import waveform_generator, make_wavgen_ios from param_loading import (get_nibbles, DaisyChain, bitfields, daisy_chain_driver, param_clock_driver) from output_stage import delta_sigma_dac from amps_filters import vca from envgen import adsr from config import (MHZ, AUDIO_RATE, DIVIDER, N, WHOLE, HALF, MASK, SECOND, compute_delta_phase, unsigned_bus, signed_bus, signed_to_unsigned, unsigned_to_signed) A_ABOVE_MIDDLE_C = compute_delta_phase(440) DELTA_PHASE = A_ABOVE_MIDDLE_C def make_fpga_ios(): fastclk = Signal(False) reset = Signal(False) param_data = unsigned_bus(4) param_clk = Signal(False) audio_req = Signal(False) audio_ack = Signal(False) dac_bit = Signal(True) return (fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit)