def test_reg_addr_align_custom(self):
"""Test of adding register with address not aligned to a proper value (based on a custom value)."""
config = Configuration()
config['regmap']['address_alignment_mode'].value = 'custom'
config['regmap']['address_alignment_value'].value = 128
rmap = RegisterMap(config=config)
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_a', 'Register A', 0x4))
def test_reg_addr_order(self):
"""Test of adding registers and check that they are presented in ascending order in a map."""
rmap = RegisterMap()
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
rmap.add_regs(Register('reg_b', 'Register B', 0x10))
rmap.add_regs(Register('reg_c', 'Register C', 0x4))
rmap.add_regs(Register('reg_d', 'Register D', 0x14))
assert rmap.names == ['reg_a', 'reg_c', 'reg_b', 'reg_d']
def test_reg_addr_align_data_width(self):
"""Test of adding register with address not aligned to a proper value (based on a data width)."""
config = Configuration()
config['regmap']['address_alignment_mode'].value = 'data_width'
config['data_width'].value = 32
rmap = RegisterMap(config=config)
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_a', 'Register A', 0x2))
def test_reg_addr_align_none(self):
"""Test of adding register with address not aligned to a proper value (based on a custom value)."""
config = Configuration()
config['regmap']['address_alignment_mode'].value = 'none'
config['data_width'].value = 32
config['regmap']['address_alignment_value'].value = 128
rmap = RegisterMap(config=config)
# no exception
rmap.add_regs(Register('reg_a', 'Register A', 0x2))
def test_bf_datawidth_conflict(self):
"""Wait exception when bf.msb value exceeds data width."""
reg = Register('reg_a', 'Register A', 0x4)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0, width=35),
])
rmap = RegisterMap()
with pytest.raises(ValueError):
rmap.add_regs(reg)
def test_add_regs(self):
"""Test of adding several registers to a map"""
reg_a = Register('reg_a', 'Register A', 0x8)
reg_b = Register('reg_b', 'Register B', 0xC)
rmap = RegisterMap()
rmap.add_regs([reg_a, reg_b])
assert rmap[0] == reg_a
assert rmap['reg_a'] == reg_a
assert rmap[1] == reg_b
assert rmap['reg_b'] == reg_b
def test_compl(self):
"""Add complementary pair to register map."""
rmap = RegisterMap()
rmap.add_regs([
Register('rega_w',
'Register A write part',
0x0,
complementary=True),
Register('rega_r', 'Register A read part', 0x0,
complementary=True),
])
def test_eq(self):
"""Test of equality comparision of register maps."""
reg = Register('reg_a', 'Register A', 0x4)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0),
BitField('bf_b', 'Bit field B', lsb=1)
])
rmap1 = RegisterMap()
rmap1.add_regs(reg)
rmap2 = copy.deepcopy(rmap1)
assert rmap1 == rmap2
def test_reg_addr_string(self):
"""Test of adding registers with addresses represented as hexadenical string."""
rmap = RegisterMap()
rmap.add_regs([
Register('reg_a', 'Register A', '0x04'),
Register('reg_b', 'Register B', '0x08'),
Register('reg_c', 'Register C', '0x0C'),
])
assert rmap['reg_a'].address == 0x04
assert rmap['reg_b'].address == 0x08
assert rmap['reg_c'].address == 0x0C
def test_create(self):
"""Test of a register map creation."""
name = 'reg_a'
description = 'Register A'
address = 0x4
reg = Register(name, description, address)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0),
BitField('bf_b', 'Bit field B', lsb=1)
])
rmap = RegisterMap()
rmap.add_regs(reg)
print(repr(rmap))
print(rmap)
assert rmap['reg_a'] == reg
def _write(self, path):
# create regmap
rmap_orig = RegisterMap()
# write to file
RegisterMapWriter()(path, rmap_orig)
# read back
rmap_test = RegisterMapReader()(path)
assert rmap_test == rmap_orig
def test_compl_no_addr(self):
"""Address of a complementary registers must be assigned explicitly"""
reg = Register('reg_a', 'Register A', complementary=True)
rmap = RegisterMap()
rmap.config['regmap']['address_increment_mode'].value = 'data_width'
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_b', 'Register B', complementary=True))
def test_verilog_write(self, tmpdir):
"""Test of creating regmap module in Verilog."""
output_file = str(tmpdir.join('regs.v'))
print('output_file:', output_file)
# create regmap
rmap = RegisterMap()
# write output file
writer = HdlWriter()
writer(output_file, rmap)
# read file and verify
with open(output_file, 'r') as f:
raw_str = ''.join(f.readlines())
assert 'module regs' in raw_str
assert 'endmodule' in raw_str
def test_reg_addr_auto_incr_data_width(self):
"""Test of auto increment of a register's address based on interface data width."""
config = Configuration()
config['regmap']['address_increment_mode'].value = 'data_width'
config['data_width'].value = 64
rmap = RegisterMap(config=config)
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
rmap.add_regs(Register('reg_b', 'Register B'))
assert rmap['reg_b'].address == 0x8
def test_compl_multiple(self):
"""Wait exception when more then 2 complementary registers are assigned to the one address."""
rmap = RegisterMap()
rmap.add_regs(
Register('rega_w',
'Register A write part',
0x0,
complementary=True))
rmap.add_regs(
Register('rega_r', 'Register A read part', 0x0,
complementary=True))
with pytest.raises(ValueError):
rmap.add_regs(
Register('rega_rr',
'Register A one more read part',
0x0,
complementary=True))
def test_wlock_ro(self):
"""Exception when write_lock is active in register with no write bitfields."""
reg = Register('rega', 'Register A', 0x0, write_lock=True)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0, width=16, access='ro'),
])
rmap = RegisterMap()
rmap.add_regs(reg)
with pytest.raises(ValueError):
rmap._validate()
def test_compl_orphan(self):
"""Wait exception when no complementary pair found after validation"""
reg = Register('reg_a', 'Register A', 0x4, complementary=True)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0, width=16, access='ro'),
])
rmap = RegisterMap()
rmap.add_regs(reg)
with pytest.raises(ValueError):
rmap._validate()
def test_compl_wr(self):
"""Wait exception when there is at least one RW field in complementary register"""
reg = Register('reg_a', 'Register A', 0x4, complementary=True)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0, width=16, access='rw'),
])
rmap = RegisterMap()
rmap.add_regs(reg)
with pytest.raises(ValueError):
rmap._validate()
def test_reg_addr_auto_incr_custom(self):
"""Test of auto increment of a register's address."""
config = Configuration()
config['regmap']['address_alignment_mode'].value = 'none'
config['regmap']['address_increment_mode'].value = 'custom'
config['regmap']['address_increment_value'].value = 0x2
rmap = RegisterMap(config=config)
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
rmap.add_regs(Register('reg_b', 'Register B'))
assert rmap['reg_b'].address == 0x2
def test_compl_mixed(self):
"""Wait exception when there are 'wo' and 'ro' fields inside complementary register"""
reg = Register('reg_a', 'Register A', 0x4, complementary=True)
reg.add_bfields([
BitField('bf_a', 'Bit field A', lsb=0, width=16, access='ro'),
BitField('bf_b', 'Bit field B', lsb=16, width=16, access='wo'),
])
rmap = RegisterMap()
rmap.add_regs(reg)
with pytest.raises(ValueError):
rmap._validate()
def test_reg_addr_auto_incr_align(self):
"""Test of alignment check of an auto incremented register's address."""
config = Configuration()
config['regmap']['address_alignment_mode'].value = 'custom'
config['regmap']['address_alignment_value'].value = 0x4
config['regmap']['address_increment_mode'].value = 'custom'
config['regmap']['address_increment_value'].value = 0x2
rmap = RegisterMap(config=config)
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_b', 'Register B'))
def test_reg_name_conflict(self):
"""Test of adding register with a name that already present in a map."""
rmap = RegisterMap()
rmap.add_regs(Register('reg_a', 'Register A', 0x8))
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_a', 'Register A copypaste', 0x8))
def test_reg_no_addr_first(self):
"""Test of adding first register with no address to a map"""
rmap = RegisterMap()
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_a', 'Register A'))
def test_reg_no_addr_no_incr(self):
"""Test of adding register with no address to a map when address auto increment is deisabled."""
rmap = RegisterMap()
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_b', 'Register B'))
def test_reg_addr_conflict(self):
"""Test of adding register with an address that already present in a map."""
rmap = RegisterMap()
rmap.add_regs(Register('reg_a', 'Register A', 0x0))
with pytest.raises(ValueError):
rmap.add_regs(Register('reg_b', 'Register B', 0x0))
