def __init__(self, d0: Logic, d1: Logic, d2: Logic, d3: Logic, sel: Logic, y: Logic):
# separa os bits do sel
sel0, sel1 = Logic(1), Logic(1)
LogicBitsSplitter(sel, [sel0, sel1])
# conecta 3 mux2 para format o mux4
mux0_y, mux1_y = Logic(1), Logic(1)
Mux2(d0, d1, sel0, mux0_y)
Mux2(d2, d3, sel0, mux1_y)
Mux2(mux0_y, mux1_y, sel1, y)
def create_shift_left_tvs():
a, y = Logic(32), Logic(32)
sl = ShiftLeft32(a, y)
# a_y
file = open('../simulation/modelsim/shift_left32.tv', 'w')
# testa com 20 numeros aleatorios
for _ in range(20):
a.set(randint(0, 0xFFFFFFFF))
sl.write_in(file)
file.close()
def create_decoder_tvs():
a = Logic(5)
y = Logic(32)
decoder = Decoder5x32(a, y)
# d0_d1_sel_y
file = open('../simulation/modelsim/decoder5x32.tv', 'w')
for i in range(0b00000, 0b11111 + 1):
a.set(i)
decoder.write_in(file)
file.close()
def create_mux8_tvs():
d, sel, y = Logic(8), Logic(3), Logic(1)
Mux8(d, sel, y)
# d0_d1_d2_d3_sel_y
file = open('../simulation/modelsim/mux8.tv', 'w')
def write_vector():
file.write('{:08b}_{:03b}_{:01b}\n'.format(d, sel, y))
# test only selected = 1
for dsel in range(8):
data = 1 << dsel
sel.set(dsel)
d.set(data)
write_vector()
# test only selected = 0
for dsel in range(8):
data = ~(1 << dsel) & (2**8 - 1)
sel.set(dsel)
d.set(data)
write_vector()
file.close()
def __init__(self, d: Logic, sel: Logic, y: Logic):
if d.n_bits != 8 or sel.n_bits != 3 or y.n_bits != 1:
raise ValueError()
# separa os bits do d
ds: List[Logic] = [Logic(1) for _ in range(8)]
LogicBitsSplitter(d, ds)
# separa os bits do sel
sels: List[Logic] = [Logic(1) for _ in range(3)]
LogicBitsSplitter(sel, sels)
ymux = [Logic(1), Logic(1)] # saida dos mux 4
selm1 = Logic(2)
LogicBitsJoiner(sels[0:2], selm1)
for m in range(2):
Mux4(ds[4 * m + 0], ds[4 * m + 1], ds[4 * m + 2], ds[4 * m + 3],
selm1, ymux[m])
# mux2 no final
Mux2(ymux[0], ymux[1], sels[2], y)
def create_full_adder_tvs():
a, b, cin, y, cout = Logic(1), Logic(1), Logic(1), Logic(1), Logic(1)
fa = FullAdder(a=a, b=b, cin=cin, s=y, cout=cout)
file = open('../simulation/modelsim/full_adder.tv', 'w')
for i1 in [0, 1]:
a.set(i1)
for i2 in [0, 1]:
b.set(i2)
for c in [0, 1]:
cin.set(c)
fa.write_in(file)
file.close()
def __init__(self, d: Logic, sel: Logic, y: Logic):
# separa os 32 bits do d
ds: List[Logic] = [Logic(1) for _ in range(32)]
LogicBitsSplitter(d, ds)
# separa os bits do sel
sels: List[Logic] = [Logic(1) for _ in range(5)]
LogicBitsSplitter(sel, sels)
# saida dos mux intermediarios
ymux1: List[Logic] = [Logic(1) for _ in range(8)]
ymux2: List[Logic] = [Logic(1) for _ in range(2)]
# primeira camada de muxes
selm1 = Logic(2)
LogicBitsJoiner(sels[0:2], selm1)
for m in range(8):
Mux4(ds[4 * m + 0], ds[4 * m + 1], ds[4 * m + 2], ds[4 * m + 3],
selm1, ymux1[m])
# segunda camada de bits
selm2 = Logic(2)
LogicBitsJoiner(sels[2:4], selm2)
for m in range(2):
Mux4(ymux1[4 * m + 0], ymux1[4 * m + 1], ymux1[4 * m + 2],
ymux1[4 * m + 3], selm2, ymux2[m])
# ultimo mux
Mux2(ymux2[0], ymux2[1], sels[4], y)
def create_mux2_tvs():
d0, d1, sel, y = Logic(1), Logic(1), Logic(1), Logic(1)
mux2 = Mux2(d0, d1, sel, y)
# d0_d1_sel_y
file = open('../simulation/modelsim/mux2.tv', 'w')
for id0 in [0, 1]:
d0.set(id0)
for id1 in [0, 1]:
d1.set(id1)
for isel in [0, 1]:
sel.set(isel)
mux2.write_in(file)
file.close()
def create_sign_extend_tvs():
a, y = Logic(16), Logic(32)
se = SignExtend16(a, y)
# a_y
file = open('../simulation/modelsim/sign_extend16.tv', 'w')
# testa 10 numeros positivos aleatorios
for _ in range(10):
a.set(randint(0, 0x7FFF))
se.write_in(file)
# testa 10 numeros negativos aleatorios
for _ in range(10):
a.set(randint(0x8000, 0xFFFF))
se.write_in(file)
file.close()
def __init__(self, a: Logic, b: Logic, op: Logic, slt_in: Logic,
adder_cin: Logic, adder_cout: Logic, adder_s: Logic,
result: Logic):
and_out, or_out, nor_out, xor_out = Logic(1), Logic(1), Logic(
1), Logic(1)
And(a, b, and_out)
Or(a, b, or_out)
Nor(a, b, nor_out)
Xor(a, b, xor_out)
op_bits: List[Logic] = [Logic(1) for _ in range(3)]
LogicBitsSplitter(op, op_bits) # divide bits do op
adder_b = Logic(1)
Xor(b, op_bits[0], adder_b) # se op = sub nega o b
FullAdder(a=a, b=adder_b, cin=adder_cin, s=adder_s, cout=adder_cout)
muxIn, zero = Logic(8), Logic(1)
zero.set(0)
LogicBitsJoiner([
and_out, or_out, adder_s, xor_out, zero, nor_out, adder_s, slt_in
], muxIn)
Mux8(muxIn, op, result)
def create_alu_tvs():
a, b, op, slt = Logic(1), Logic(1), Logic(3), Logic(1)
adder_cin, adder_cout, adder_s = Logic(1), Logic(1), Logic(1)
slt.set(0)
result = Logic(1)
ALU(a, b, op, slt, adder_cin, adder_cout, adder_s, result)
# d0_d1_d2_d3_sel_y
file = open('../simulation/modelsim/alu.tv', 'w')
def write_vector():
file.write(
'{:01b}_{:01b}_{:03b}_{:01b}_{:01b}_{:01b}_{:01b}_{:01b}\n'.format(
a, b, op, slt, adder_cin, adder_cout, adder_s, result))
for iop in [0b010, 0b110, 0b000, 0b001, 0b101, 0b011,
0b111]: # testa vez cada operacao
op.set(iop)
for ia in [0, 1]:
a.set(ia)
for ib in [0, 1]:
b.set(ib)
for icin in [0, 1]:
adder_cin.set(icin)
write_vector()
file.close()
def create_mux4_tvs():
d0, d1, d2, d3 = Logic(1), Logic(1), Logic(1), Logic(1)
sel, y = Logic(2), Logic(1)
Mux4(d0, d1, d2, d3, sel, y)
# d0_d1_d2_d3_sel_y
file = open('../simulation/modelsim/mux4.tv', 'w')
def write_vector():
file.write('{}_{}_{}_{}_{:02b}_{}\n'.format(d0, d1, d2, d3, sel, y))
for id0 in [0, 1]:
d0.set(id0)
for id1 in [0, 1]:
d1.set(id1)
for id2 in [0, 1]:
d2.set(id2)
for id3 in [0, 1]:
d3.set(id3)
for isel in range(4):
sel.set(isel)
write_vector()
file.close()
def add_input(self, name: str, a: Logic):
if name in self.inputs:
self.inputs[name].remove_listener(self)
self.inputs[name] = a
a.listen(self)
def create_flopenr_tvs():
clk, en, rst, d, q = Logic(1), Logic(1), Logic(1), Logic(1), Logic(1)
flopenr = FlopEnR(clk, en, rst, d, q)
# clk_en_rst_d_q
out = open('../simulation/modelsim/flopenr.tv', 'w')
# init
clk.set(0), en.set(1), rst.set(0), d.set(0), flopenr.write_in(out)
# test reset
en.set(1), rst.set(1), d.set(1), clk.set(1), flopenr.write_in(out)
clk.set(0), flopenr.write_in(out)
clk.set(1), flopenr.write_in(out)
rst.set(0)
# test enable = 0
en.set(0), clk.set(0), flopenr.write_in(out)
clk.set(1), flopenr.write_in(out)
en.set(1)
# test data
for i in range(15): # gera 15 casos de teste
if randint(0, 2) == 0: # inverte dado 1/3 de chance
data = 1 - d.data
d.set(data)
else: # inverte clock 2/3 de chance
clock = 1 - clk.data
clk.set(clock)
# x_clk_y
flopenr.write_in(out)
out.close()