def make_mlc(channel_type, tp): if channel_type is "FAC": # 4-QAM return drm_mlc_4qam_bc(bits_per_symbol=tp.fac().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.fac().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.fac().punct_pat_0(), pp_tail=tp.fac().punct_pat_0(), vlen_in=tp.fac().L(), vlen_out=tp.fac().N()) elif channel_type is "SDC": # 16-QAM if tp.cfg().sdc_mapping() == 0: return drm_mlc_16qam_bc( vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.sdc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.sdc().punct_pat_0(), interl_seq_0_2=tp.sdc().bit_interl_seq_0_2(), interl_seq_1_2=tp.sdc().bit_interl_seq_1_2(), pp_1_tail=tp.sdc().punct_pat_tail_1(), pp_1=tp.sdc().punct_pat_1(), pp_0_tail=tp.sdc().punct_pat_tail_0(), M_total=tp.sdc().M_total(), part_len_top=tp.sdc().M_total()[0], part_len_bot=tp.sdc().M_total()[1], ) elif tp.cfg().sdc_mapping() == 1: return drm_mlc_4qam_bc( bits_per_symbol=tp.sdc().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.sdc().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.sdc().punct_pat_0(), pp_tail=tp.sdc().punct_pat_tail_0(), vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N()) else: raise RuntimeError("Invalid SDC modulation order: " + str(tp.sdc().mod_order())) elif channel_type is "MSC": if tp.cfg().msc_mapping( ) == 0: # FIXME This is likely to be an errouneous configuration! Only relevant for DRM+, though return drm_mlc_4qam_bc( bits_per_symbol=tp.msc().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.msc().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.msc().punct_pat_0_2(), pp_tail=tp.msc().punct_pat_0_2(), vlen_in=tp.msc().L_MUX(), vlen_out=tp.msc().N_MUX()) elif tp.cfg().msc_mapping() == 1: return drm_mlc_16qam_bc( vlen_in=tp.msc().L_MUX(), vlen_out=tp.msc().N_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.msc().punct_pat_0_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_1=tp.msc().punct_pat_1_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), M_total=tp.msc().M_total(), part_len_top=tp.msc().M_total()[0], part_len_bot=tp.msc().M_total()[1], ) elif tp.cfg().msc_mapping() == 2: return drm_mlc_64qam_sm_bc( vlen_in=tp.msc().L_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), vlen_out=tp.msc().N_MUX(), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM64SM, pp_0=tp.msc().punct_pat_0_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), pp_1=tp.msc().punct_pat_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_2=tp.msc().punct_pat_2_2(), pp_2_tail=tp.msc().punct_pat_tail_2_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_2_2=tp.msc().bit_interl_seq_2_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), M_total=tp.msc().M_total(), part_len_bot=tp.msc().M_total()[2], part_len_top=tp.msc().M_total()[0], part_len_mid=tp.msc().M_total()[1], ) else: print("MSC Mapping:", tp.cfg().msc_mapping()) raise RuntimeError("Invalid MSC modulation order: " + str(tp.msc().mod_order())) else: raise RuntimeError("Invalid channel type:", channel_type)
def __init__(self,DRMParameters): gr.top_block.__init__(self, "DRM Transmitter 1") ################################################## # Variables ################################################## self.text_message = text_message = DRMParameters.text_msg self.station_label = station_label = DRMParameters.station_label self.msc_prot_level_2 = msc_prot_level_2 = 1 self.long_interl = long_interl = True self.audio_sample_rate = audio_sample_rate = DRMParameters.audio_samp*1000 self.SO = SO = DRMParameters.so self.RM = RM = DRMParameters.rm self.tp = tp = drm.transm_params(RM, SO, False, 0, False, DRMParameters.msc_mod, 0, msc_prot_level_2, DRMParameters.sdc_mod, 0, long_interl, audio_sample_rate, station_label, text_message) self.samp_rate = samp_rate = 48e3 self.usrp_addr = DRMParameters.usrp_id self.output_name = DRMParameters.output_name self.center_freq = DRMParameters.center_freq*1e6 self.audio_file = DRMParameters.audio_file ################################################## # Blocks ################################################## if DRMParameters.uhd_found: self.uhd_usrp_sink_0 = uhd.usrp_sink( ",".join((self.usrp_addr, "")), uhd.stream_args( cpu_format="fc32", channels=range(1), ), ) self.uhd_usrp_sink_0.set_samp_rate(samp_rate * 250 / 48) self.uhd_usrp_sink_0.set_center_freq(self.center_freq, 0) self.uhd_usrp_sink_0.set_gain(0, 0) self.uhd_usrp_sink_0.set_antenna("TXA", 0) self.rational_resampler_xxx_0 = filter.rational_resampler_ccc( interpolation=250, decimation=48, taps=None, fractional_bw=None, ) self.fft_vxx_0 = fft.fft_vcc(tp.ofdm().nfft(), False, (), True, 1) self.drm_scrambler_bb_0_1 = drm.scrambler_bb(tp.sdc().L()) self.drm_scrambler_bb_0_0 = drm.scrambler_bb(tp.fac().L()) self.drm_scrambler_bb_0 = drm.scrambler_bb(tp.msc().L_MUX()) self.drm_mlc_4qam_bc_0_0 = drm_mlc_4qam_bc( bits_per_symbol=tp.fac().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), interl_seq=tp.fac().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.fac().punct_pat_0(), pp_tail=tp.fac().punct_pat_0(), vlen_in=tp.fac().L(), vlen_out=tp.fac().N(), ) #SDC Configuration if DRMParameters.sdc_mod == 0: self.drm_mlc_sdc_bc= drm_mlc_16qam_bc( vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.sdc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.sdc().punct_pat_0(), interl_seq_0_2=tp.sdc().bit_interl_seq_0_2(), interl_seq_1_2=tp.sdc().bit_interl_seq_1_2(), pp_1_tail=tp.sdc().punct_pat_tail_1(), pp_1=tp.sdc().punct_pat_1(), pp_0_tail=tp.sdc().punct_pat_tail_0(), M_total=tp.sdc().M_total(), part_len_top=tp.sdc().M_total()[0], part_len_bot=tp.sdc().M_total()[1], ) else: self.drm_mlc_sdc_bc = drm_mlc_4qam_bc( vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, map_tab=tp.cfg().ptables().d_QAM4, interl_seq=tp.sdc().bit_interl_seq_0_2(), bits_per_symbol=tp.sdc().mod_order(), pp=tp.sdc().punct_pat_0(), pp_tail=tp.sdc().punct_pat_tail_0(), gen_poly=(91, 121, 101, 91, 121, 101), ) #MSC Configuration if DRMParameters.msc_mod == 2: self.drm_mlc_msc_bc = drm_mlc_64qam_sm_bc( vlen_in=tp.msc().L_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), vlen_out=tp.msc().N_MUX(), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM64SM, pp_0=tp.msc().punct_pat_0_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), pp_1=tp.msc().punct_pat_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_2=tp.msc().punct_pat_2_2(), pp_2_tail=tp.msc().punct_pat_tail_2_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_2_2=tp.msc().bit_interl_seq_2_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), M_total=tp.msc().M_total(), part_len_bot=tp.msc().M_total()[2], part_len_top=tp.msc().M_total()[0], part_len_mid=tp.msc().M_total()[1], ) else: self.drm_mlc_msc_bc = drm_mlc_16qam_bc( vlen_in=tp.msc().L_MUX(), vlen_out=tp.msc().N_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.msc().punct_pat_0_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_1=tp.msc().punct_pat_1_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), M_total=tp.msc().M_total(), part_len_top=tp.msc().M_total()[0], part_len_bot=tp.msc().M_total()[1], ) self.drm_interleaver_cc_0 = drm.interleaver_cc((tp.msc().cell_interl_seq()), long_interl, drm.INTL_DEPTH_DRM) self.drm_generate_sdc_b_0 = drm.generate_sdc_b(tp) self.drm_generate_fac_b_0 = drm.generate_fac_b(tp) self.drm_audio_encoder_sb_0 = drm.audio_encoder_sb(tp) self.digital_ofdm_cyclic_prefixer_1 = digital.ofdm_cyclic_prefixer(tp.ofdm().nfft(), tp.ofdm().nfft()+tp.ofdm().nfft()/4, 0, "") self.cell_mapping_cc_0 = drm.cell_mapping_cc(tp, (tp.msc().N_MUX() * tp.ofdm().M_TF() * 8, tp.sdc().N() * 8, tp.fac().N() * tp.ofdm().M_TF() * 8)) self.blocks_null_sink_0 = blocks.null_sink(gr.sizeof_float*1) if DRMParameters.pulse_audio: self.audio_source_1 = audio.source(audio_sample_rate, "", True) else: self.blocks_wavfile_source_0 = blocks.wavfile_source(self.audio_file, False) if DRMParameters.gen_output: self.blocks_wavfile_sink_0 = blocks.wavfile_sink(self.output_name, 1, 48000, 16) self.blocks_multiply_xx_0 = blocks.multiply_vcc(1) self.blocks_multiply_const_vxx_1 = blocks.multiply_const_vcc((7e-3, )) self.blocks_multiply_const_vxx_0 = blocks.multiply_const_vff((32768, )) self.blocks_complex_to_real_0 = blocks.complex_to_real(1) self.analog_sig_source_x_0 = analog.sig_source_c(samp_rate, analog.GR_COS_WAVE, 7000, 1, 0) ################################################## # Connections ################################################## self.connect((self.analog_sig_source_x_0, 0), (self.blocks_multiply_xx_0, 1)) if DRMParameters.gen_output: self.connect((self.blocks_complex_to_real_0, 0), (self.blocks_wavfile_sink_0, 0)) self.connect((self.blocks_multiply_const_vxx_0, 0), (self.drm_audio_encoder_sb_0, 0)) self.connect((self.blocks_multiply_const_vxx_1, 0), (self.blocks_multiply_xx_0, 0)) self.connect((self.blocks_multiply_xx_0, 0), (self.blocks_complex_to_real_0, 0)) if DRMParameters.pulse_audio: self.connect((self.audio_source_1, 0), (self.blocks_multiply_const_vxx_0, 0)) else: self.connect((self.blocks_wavfile_source_0, 0), (self.blocks_multiply_const_vxx_0, 0)) self.connect((self.cell_mapping_cc_0, 0), (self.fft_vxx_0, 0)) self.connect((self.digital_ofdm_cyclic_prefixer_1, 0), (self.blocks_multiply_const_vxx_1, 0)) self.connect((self.drm_audio_encoder_sb_0, 0), (self.drm_scrambler_bb_0, 0)) self.connect((self.drm_generate_fac_b_0, 0), (self.drm_scrambler_bb_0_0, 0)) self.connect((self.drm_generate_sdc_b_0, 0), (self.drm_scrambler_bb_0_1, 0)) self.connect((self.drm_interleaver_cc_0, 0), (self.cell_mapping_cc_0, 0)) self.connect((self.drm_mlc_msc_bc, 0), (self.drm_interleaver_cc_0, 0)) self.connect((self.drm_mlc_sdc_bc, 0), (self.cell_mapping_cc_0, 1)) self.connect((self.drm_mlc_4qam_bc_0_0, 0), (self.cell_mapping_cc_0, 2)) self.connect((self.drm_scrambler_bb_0, 0), (self.drm_mlc_msc_bc, 0)) self.connect((self.drm_scrambler_bb_0_0, 0), (self.drm_mlc_4qam_bc_0_0, 0)) self.connect((self.drm_scrambler_bb_0_1, 0), (self.drm_mlc_sdc_bc, 0)) self.connect((self.fft_vxx_0, 0), (self.digital_ofdm_cyclic_prefixer_1, 0)) if DRMParameters.uhd_found: self.connect((self.rational_resampler_xxx_0, 0), (self.uhd_usrp_sink_0, 0)) self.connect((self.blocks_multiply_const_vxx_1, 0), (self.rational_resampler_xxx_0, 0)) self.connect((self.blocks_complex_to_real_0, 0), (self.blocks_null_sink_0, 0))
def make_mlc(channel_type, tp): if channel_type is "FAC": # 4-QAM return drm_mlc_4qam_bc( bits_per_symbol=tp.fac().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.fac().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.fac().punct_pat_0(), pp_tail=tp.fac().punct_pat_0(), vlen_in=tp.fac().L(), vlen_out=tp.fac().N(), ) elif channel_type is "SDC": # 16-QAM if tp.cfg().sdc_mapping() == 0: return drm_mlc_16qam_bc( vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.sdc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.sdc().punct_pat_0(), interl_seq_0_2=tp.sdc().bit_interl_seq_0_2(), interl_seq_1_2=tp.sdc().bit_interl_seq_1_2(), pp_1_tail=tp.sdc().punct_pat_tail_1(), pp_1=tp.sdc().punct_pat_1(), pp_0_tail=tp.sdc().punct_pat_tail_0(), M_total=tp.sdc().M_total(), part_len_top=tp.sdc().M_total()[0], part_len_bot=tp.sdc().M_total()[1], ) elif tp.cfg().sdc_mapping() == 1: return drm_mlc_4qam_bc( bits_per_symbol=tp.sdc().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.sdc().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.sdc().punct_pat_0(), pp_tail=tp.sdc().punct_pat_0(), vlen_in=tp.sdc().L(), vlen_out=tp.sdc().N(), ) else: raise RuntimeError("Invalid SDC modulation order: " + str(tp.sdc().mod_order())) elif channel_type is "MSC": if ( tp.cfg().msc_mapping() == 0 ): # FIXME This is likely to be an errouneous configuration! Only relevant for DRM+, though return drm_mlc_4qam_bc( bits_per_symbol=tp.msc().mod_order(), denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=gen_poly, interl_seq=tp.msc().bit_interl_seq_0_2(), map_tab=tp.cfg().ptables().d_QAM4, n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, pp=tp.msc().punct_pat_0_2(), pp_tail=tp.msc().punct_pat_0_2(), vlen_in=tp.msc().L_MUX(), vlen_out=tp.msc().N_MUX(), ) elif tp.cfg().msc_mapping() == 1: return drm_mlc_16qam_bc( vlen_in=tp.msc().L_MUX(), vlen_out=tp.msc().N_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM16, pp_0=tp.msc().punct_pat_0_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_1=tp.msc().punct_pat_1_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), M_total=tp.msc().M_total(), part_len_top=tp.msc().M_total()[0], part_len_bot=tp.msc().M_total()[1], ) elif tp.cfg().msc_mapping() == 2: return drm_mlc_64qam_sm_bc( vlen_in=tp.msc().L_MUX(), n_tailbits=drm.N_TAILBITS / drm.DENOM_MOTHER_CODE, denom_mother_code_rate=drm.DENOM_MOTHER_CODE, gen_poly=(91, 121, 101, 91, 121, 101), vlen_out=tp.msc().N_MUX(), bits_per_symbol=tp.msc().mod_order(), map_tab=tp.cfg().ptables().d_QAM64SM, pp_0=tp.msc().punct_pat_0_2(), pp_0_tail=tp.msc().punct_pat_tail_0_2(), pp_1=tp.msc().punct_pat_1_2(), pp_1_tail=tp.msc().punct_pat_tail_1_2(), pp_2=tp.msc().punct_pat_2_2(), pp_2_tail=tp.msc().punct_pat_tail_2_2(), interl_seq_0_2=tp.msc().bit_interl_seq_0_2(), interl_seq_2_2=tp.msc().bit_interl_seq_2_2(), interl_seq_1_2=tp.msc().bit_interl_seq_1_2(), M_total=tp.msc().M_total(), part_len_bot=tp.msc().M_total()[2], part_len_top=tp.msc().M_total()[0], part_len_mid=tp.msc().M_total()[1], ) else: print("MSC Mapping:", tp.cfg().msc_mapping()) raise RuntimeError("Invalid MSC modulation order: " + str(tp.msc().mod_order())) else: raise RuntimeError("Invalid channel type:", channel_type)