def voltage_divider_test():
# voltage divider examples from datasheet.
#if voltage == 1.8:
# 80.6k, 64.9k
#if voltage == 2.5
# 49.9k, 23.7k
#if voltage == 3.3:
# 49.9, 16.2k
#if voltage == 5.0:
# 49.9, 9.53k
# voltage_divider("feedback_divider", "49.9k", "16.2k", high=v_out, low=gnd, output=u.pin_nets["fb"]) # feedback current is "0.1uA", calculate rest automatically?
gnd = scoped_net("gnd")
voltage_divider_auto("feedback_divider",
idle_current="0.05m",
input_voltage=3.3,
output_voltage=0.81,
high=net(),
low=gnd,
output=scoped_net("output"))
assert False
# About: 10kΩ + 3.24kΩ
voltage_divider_auto("feedback_divider",
idle_current="0.4m",
input_voltage=5,
output_voltage=1.221,
high=net(),
low=gnd,
output=scoped_net("output"))
assert False
def myschematic():
psu1 = sub(psu, lm7805)
psu2 = sub(psu, lm7809)
v_in = net("v_in_20V") # 20V nominal
gnd = GND()
# Parametrically create a DC-DC converter circuit, automatically computing all
# paramters from requirements, and placing auxilary components.
dc1 = sub(dcdc_mp2359_full,
"dcdc3.3V",
v_in=v_in,
gnd=gnd,
v_out=net(),
output_voltage="3.3V",
max_output_current="1.2A",
min_input_voltage="12V",
max_input_voltage="25V",
en_pullup=True,
external_bootstrap_diode=False,
opt_d3=True)
dc2 = sub(
dcdc_tps543x_full,
"dcdc5V",
v_in=v_in,
gnd=gnd,
v_out=net(),
output_voltage="5V",
max_current="2A",
min_input_voltage="10V",
max_input_voltage="24V",
en_pullup=True,
external_bootstrap_diode=True,
all_ceramic_output_filter_caps=True,
inductance="16µH") # Default of 15µH is a bit too low, causes assert.
#print(dc2.nets["v_out"])
# whatever, do something silly with the sub-components.
#ucap("silly_capacitor", "1uF", dc1.out, dc2.out)
osc = oscilator("16M")
def voltage_divider(name: str,
*,
r_high: 'Ohm',
r_low: 'Ohm',
high: 'NET',
low: 'NET',
output: 'NET' = None,
accuracy: '%' = 1):
"""Accuracy is used to select standard series resistors for the divider.
If better accuracy is needed, a combinations of resistors will be used.
TODO(baryluk): Quantize to R24, R48, R92 series.
"""
# TODO: Scope(name)
assert accuracy > 0.0
output = output if output else net()
res("r_high", r_high, a=high, b=output)
res("r_low", r_low, a=output, b=low)
return output
def psu(regulator=lm7805, gnd=None):
gnd = gnd if gnd else GND()
input, output = scoped_net("input"), scoped_net("output")
with note("psu"):
with warning(
"capacitors at least 5mm way from regulator for heat reasons"):
cap("input_cap", "50m", p=input, n=gnd)
regulator("voltage regulator", input=input, gnd=gnd, output=output)
cap("output cap1", "50m", p=output, n=gnd)
for caps in range(3):
cap("output cap2", "2n", p=output, n=gnd)
with note("load"):
r = res("load", "1k", a=output, b=net())
diode("load", a=r.pin_nets[1], c=gnd)
return export_nets(gnd=gnd, input=input, output=output)
# We need to create a meta-component, that is technically not registered, but
# is only used in case it is used in other parallel / series operations.
def parallel(*components):
assert len(components) >= 1
c0 = components[0]
if isinstance(c0.pin_nets, list):
pass
pass
from edag import net
from edag_components import res
R12 = parallel(res("r1", "1k", a=net(), b=net()),
res("r2", "2k", a=net(), b=net()))
R34 = parallel(res("r3", "3k", a=net(), b=net()),
res("r4", "4k", a=net(), b=net()))
R5 = parallel(R12, res("r5", "5k", a=net(), b=net()))
RAll = parallel(R12, R34, R5)
parallel(R12, R12) # This is the tricky one. That is very tricky.
# This one can be probably detected, but what about other cases like:
# parallel(R1, R2)
# parallel(R2, R1)
@Scope()
def oscilator(frequency: 'HZ' = "16M",
/,
load_capacitors: 'F' = "12p",
feed_resistance: 'Ohm' = 47,
gnd=None):
gnd = gnd if gnd else GND()
with note("oscilator_" + str(frequency)):
# with Scope() as scope:
a = scoped_net() # same as net(), if there is no name provided
b = scoped_net()
load_capacitance = load_capacitors
crystal("crystal", value=frequency, gnd=gnd, a=a, b=b)
ucap("load_cap_1", load_capacitance, a=a, b=gnd)
ucap("load_cap_2", load_capacitance, a=b, b=gnd)
r = res("feed_resistor", feed_resistance, a=b, b=net())
return export_nets(input=a, output=r.pin_nets[1])
@note("myschematic")
def myschematic():
psu1 = sub(psu, lm7805)
psu2 = sub(psu, lm7809)
v_in = net("v_in_20V") # 20V nominal
gnd = GND()
# Parametrically create a DC-DC converter circuit, automatically computing all
# paramters from requirements, and placing auxilary components.
dc1 = sub(dcdc_mp2359_full,
This takes into account the color, as well non-linearities at low currents.
"""
current = tofloat_I(current)
assert current > 0.0
voltage = tofloat_V(voltage)
assert voltage > 0.0
pass
def switch(name: str, a: 'NET', b: 'NET', *, omentary: bool = True):
"""Switch"""
return make_component(name, "SW", [a, b], [], {"momentary": momentary})
GND = net("GND")
def switch_with_pullup(name: str,
*,
sw: 'NET',
gnd: 'NET' = GND,
momentary: bool = True,
resistance: 'Ohm' = "5k"):
"""Switch with a pullup resistor"""
voltage = tofloat_R(resistance)
assert voltage > 0.0
pass
def fuse(name: str, a: 'NET', b: 'NET', *, current: 'A' = 1, type="polyfuse"):