class Axi4AudioAnalyzer(object): def __init__(self, name): self.name = name self.reg_num = 65536 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() self.__k1_index = 0 self.__k1_data = 0 self.__k2_index = 0 self.__k2_data = 0 self.__decimation_data = 1 self.__base_frequency = 1000 def enable(self): """enable function""" self.disable() rd_data = self.__axi4lite.read(0x10, 1) rd_data[0] = rd_data[0] | 0x01 self.__axi4lite.write(0x10, rd_data, 1) return None def disable(self): """disable function""" rd_data = self.__axi4lite.read(0x10, 1) rd_data[0] = rd_data[0] & 0xFE self.__axi4lite.write(0x10, rd_data, 1) return None def upload_enable(self): """enable data upload function""" rd_data = self.__axi4lite.read(0x10, 1) rd_data[0] = rd_data[0] | 0x02 self.__axi4lite.write(0x10, rd_data, 1) return None def upload_disable(self): """disbale data upload function""" rd_data = self.__axi4lite.read(0x10, 1) rd_data[0] = rd_data[0] & 0xFD self.__axi4lite.write(0x10, rd_data, 1) return None def measure_paramter_set(self, bandwidth_hz, sample_rate, decimation_type, signal_source): """ Set measure paramter Args: bandwidth_hz(int): Bandwidth limit, unit is Hz sample_rate(int): signal sample rate, unit is Hz decimation_type(str): signal decimation type 'auto' -- automatic detection '1'/'2'/........ signal_source(str): 'IIS'/'PDM'/'SPDIF' Returns: False | True """ wr_data = self.__data_deal.int_2_list(int(sample_rate / 1000), 3) self.__axi4lite.write(0xF0, wr_data, len(wr_data)) rd_data = self.__axi4lite.read(0x16, 1) freq_resolution = sample_rate / (8192 * rd_data[0]) bandwidth_index = int(bandwidth_hz / freq_resolution) if (signal_source == 'IIS'): source_data = 0x10 elif (signal_source == 'SPDIF'): source_data = 0x20 elif (signal_source == 'PDM'): source_data = 0x30 else: logger.error('@%s: Signal Source Error' % (self.name)) return False wr_data = self.__data_deal.int_2_list(bandwidth_index, 2) wr_data[1] = (wr_data[1] & 0x0F) | source_data self.__axi4lite.write(0x11, wr_data, len(wr_data)) self._decimation_factor_set(decimation_type) return True def measure_start(self): """ start measure Args: None Returns: False | True """ self.__axi4lite.write(0x14, [0x00], 1) self.__axi4lite.write(0x13, [0x01], 1) rd_data = [0] timeout_cnt = 0 while (rd_data[0] == 0x00) and timeout_cnt < 3000: sleep(0.001) rd_data = self.__axi4lite.read(0x14, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 3000): logger.error('@%s: wait time out' % (self.name)) return False self._base_index_find() return True def _decimation_factor_set(self, decimation_type): if (decimation_type is 'auto'): decimation_type_data = 0xFF else: decimation_type_data = int(decimation_type) self.__axi4lite.write(0x15, [decimation_type_data], 1) self.__axi4lite.write(0x17, [0x01], 1) rd_data = [0] timeout_cnt = 0 while (rd_data[0] == 0x00) and timeout_cnt < 3000: sleep(0.001) rd_data = self.__axi4lite.read(0x17, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 3000): logger.error('@%s: wait time out' % (self.name)) return False rd_data = self.__axi4lite.read(0x16, 1) self.__decimation_data = rd_data[0] return True def _max_index_find(self): rd_data = self.__axi4lite.read(0x20, 4) max_index = self.__data_deal.list_2_int(rd_data) rd_addr = 32768 + max_index * 8 rd_data = self.__axi4lite.read(rd_addr, 8) max_data = self.__data_deal.list_2_int(rd_data) return (max_index, max_data) def _base_index_find(self): (max_index, max_data) = self._max_index_find() max_left_index = max_index - 1 max_right_index = max_index + 1 rd_addr = 32768 + max_left_index * 8 rd_data = self.__axi4lite.read(rd_addr, 8) max_left_data = self.__data_deal.list_2_int(rd_data) rd_addr = 32768 + max_right_index * 8 rd_data = self.__axi4lite.read(rd_addr, 8) max_right_data = self.__data_deal.list_2_int(rd_data) if (max_left_data > max_right_data): second_index = max_left_index second_data = max_left_data else: second_index = max_right_index second_data = max_right_data if (max_index > second_index): self.__k1_index = second_index self.__k1_data = second_data self.__k2_index = max_index self.__k2_data = max_data else: self.__k2_index = second_index self.__k2_data = second_data self.__k1_index = max_index self.__k1_data = max_data return None def _get_fft_data(self, data_cnt): fft_data = [] for i in range(0, data_cnt): rd_addr = 32768 + i * 8 rd_data = self.__axi4lite.read(rd_addr, 8) rd_data_int = self.__data_deal.list_2_int(rd_data) fft_data.append(rd_data_int) return fft_data def _test_register(self, test_data): wr_data = self.__data_deal.int_2_list(test_data, 4) self.__axi4lite.write(0x00, wr_data, len(wr_data)) rd_data = self.__axi4lite.read(0x00, len(wr_data)) test_out = self.__data_deal.list_2_int(rd_data) if (test_out != test_data): logger.error('@%s: Test Register read data error. ' % (self.name)) return False return None
class Axi4TimeDetect(object): def __init__(self, name): self.name = name self.reg_num = 256 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() rd_data = self.__axi4lite.read(0x04, 4) self.__clk_frequency = self.__data_deal.list_2_int(rd_data) def disable(self): """ Disable function """ self.__axi4lite.write(0x10, [0x00], 1) return None def enable(self): """ Enable function """ self.__axi4lite.write(0x10, [0x00], 1) self.__axi4lite.write(0x10, [0x01], 1) return None def measure_disbale(self): """ Disable function """ self.__axi4lite.write(0x11, [0x00], 1) def measure_enable(self): """ Enable function """ self.__axi4lite.write(0x11, [0x00], 1) time.sleep(0.01) self.__axi4lite.write(0x11, [0x01], 1) def start_edge_set(self, start_edge_type='A-POS'): """ Set width measure start_edge_type Args: start_edge_type(str): 'A-POS' -- signal A posedge 'A-NEG' -- signal A negedge 'B-POS' -- signal B posedge 'B-NEG' -- signal B negedge 'A-P**N' -- signal A posedge or A negedge 'B-P**N' -- signal B posedge or B negedge Returns: None """ self.__axi4lite.write(0x12, [0x00], 1) if (start_edge_type == 'A-POS'): start_edge_data = 0x00 elif (start_edge_type == 'A-NEG'): start_edge_data = 0x01 elif (start_edge_type == 'B-POS'): start_edge_data = 0x02 elif (start_edge_type == 'B-NEG'): start_edge_data = 0x03 elif (start_edge_type == 'A-P**N'): start_edge_data = 0x04 elif (start_edge_type == 'B-P**N'): start_edge_data = 0x05 else: logger.error('@%s: Parameter Error' % (self.name)) return False wr_data = start_edge_data self.__axi4lite.write(0x12, [wr_data], 1) return None def stop_edge_set(self, stop_edge_type='B-POS'): """ Set width measure stop_edge_type Args: stop_edge_type(str): 'A-POS' -- signal A posedge 'A-NEG' -- signal A negedge 'B-POS' -- signal B posedge 'B-NEG' -- signal B negedge 'A-P**N' -- signal A posedge or A negedge 'B-P**N' -- signal B posedge or B negedge Returns: None """ self.__axi4lite.write(0x13, [0x00], 1) if (stop_edge_type == 'B-POS'): stop_edge_data = 0x00 elif (stop_edge_type == 'B-NEG'): stop_edge_data = 0x01 elif (stop_edge_type == 'A-POS'): stop_edge_data = 0x02 elif (stop_edge_type == 'A-NEG'): stop_edge_data = 0x03 elif (stop_edge_type == 'A-P**N'): stop_edge_data = 0x04 elif (stop_edge_type == 'B-P**N'): stop_edge_data = 0x05 else: logger.error('@%s: Parameter Error' % (self.name)) return False wr_data = stop_edge_data self.__axi4lite.write(0x13, [wr_data], 1) return None def detect_time_get(self, detect_time_ms): """ get measure data Args: None Returns: detect_data(float): the data is start_edge_type to stop_edge_type time, unit is us """ rd_data = self.__axi4lite.read(0x20, 1) detect_time_out = 0 while rd_data[0] != 0x01 and (detect_time_out < detect_time_ms + 1000): time.sleep(0.001) detect_time_out += 1 rd_data = self.__axi4lite.read(0x20, 1) if (detect_time_out == detect_time_ms + 1000): logger.error('@%s: Detect time out' % (self.name)) return False else: rd_data = self.__axi4lite.read(0x24, 4) detect_time = self.__data_deal.list_2_int(rd_data) clk_period = 1000.0 / self.__clk_frequency detect_data = clk_period * detect_time self.__axi4lite.write(0x11, [0x00], 1) return ('detect_time', detect_data, 'us')
class Axi4SpiSlave(object): def __init__(self,name): self.name = name self.reg_num = 256 self.__axi4lite=Axi4lite(self.name,self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail'%(self.name, self.reg_num)) self.__axi4_clk_frequency = 125000000 self.__data_deal = DataOperate() self.__data_width = 4 def disable(self): """ Disable function """ rd_data = self.__axi4lite.read(0x10, 1) wr_data = rd_data[0] & 0xF0 self.__axi4lite.write(0x10, [wr_data], 1) return None def enable(self): """ Enable function """ rd_data = self.__axi4lite.read(0x10, 1) wr_data = rd_data[0] & 0xF0 self.__axi4lite.write(0x10, [wr_data], 1) wr_data = rd_data[0] & 0xF0 | 0x01 self.__axi4lite.write(0x10, [wr_data], 1) return None def config(self,spi_clk_cpha_cpol = 'Mode_0',spi_byte_cfg = '1'): """ Set spi bus parameter Args: spi_byte_cfg(str): '1' --spi slave receive data or send data is 1byte '2' --spi slave receive data or send data is 2byte '3' --spi slave receive data or send data is 3byte '4' --spi slave receive data or send data is 4byte spi_clk_cpha_cpol(str): 'Mode_0' --CPHA=0, CPOL=0, when CS is high, the SCLK is low, first edge sample 'Mode_1' --CPHA=0, CPOL=1, when CS is high, the SCLK is high, first edge sample 'Mode_2' --CPHA=1, CPOL=0, when CS is high, the SCLK is low, second edge sample 'Mode_3' --CPHA=1, CPOL=1, when CS is high, the SCLK is high, second edge sample Returns: None """ mode_set_data=self.__axi4lite.write(0x11,[0x00],1) if(spi_clk_cpha_cpol == 'Mode_0'): mode_set_data = 0x00 elif(spi_clk_cpha_cpol== 'Mode_1'): mode_set_data = 0x01 elif(spi_clk_cpha_cpol== 'Mode_2'): mode_set_data = 0x02 elif(spi_clk_cpha_cpol== 'Mode_3'): mode_set_data = 0x03 else: logger.error('@%s: Mode select error'%(self.name)) return False self.__axi4lite.write(0x11, [mode_set_data], 1) self.__axi4lite.write(0x12,[0x01],1) if(spi_byte_cfg == '1'): set_byte = 0x01 elif(spi_byte_cfg == '2'): set_byte = 0x02 elif(spi_byte_cfg =='3'): set_byte = 0x03 elif(spi_byte_cfg =='4'): set_byte = 0x04 else: logger.error('@%s: byte select error'%(self.name)) return False self.__axi4lite.write(0x12, [set_byte], 1) self.__data_width=set_byte return None def register_read(self,address,read_length): read_data = [] for i in range(0,read_length): wr_data = self.__data_deal.int_2_list(address, 2) self.__axi4lite.write(0x14, wr_data, len(wr_data)) rd_data = self.__axi4lite.read(0x24,4) read_data_temp = self.__data_deal.list_2_int(rd_data) if(read_data_temp < 0): read_data_temp = read_data_temp + pow(2,32) read_data_temp = read_data_temp >> 8*(4-self.__data_width) read_data.append(read_data_temp) address = address + 1 return read_data def register_write(self,address,write_data): for i in range(0,len(write_data)): write_data_temp = write_data[i] << 8*(4-self.__data_width) wr_data = self.__data_deal.int_2_list(write_data_temp, 4) self.__axi4lite.write(0x20, wr_data, len(wr_data)) wr_data = self.__data_deal.int_2_list(address, 2) self.__axi4lite.write(0x14, wr_data, len(wr_data)) self.__axi4lite.write(0x16, [0x01], 1) address = address + 1 return None
class Axi4HdmiRreceiver(object): def __init__(self, name): self.name = name self.reg_num = 256 self.__axi4_clk_frequency = 125000000 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() self.__data_width = 4 def disable(self): """disable function""" self.__axi4lite.write(0x10, [0x00], 1) return None def enable(self): """enable function""" self.__axi4lite.write(0x10, [0x00], 1) self.__axi4lite.write(0x10, [0x01], 1) return None def initialize(self): """ initialize the edid of hdmi receiver ddc. Args: None Returns: None """ self.disable() # config ddc port paramer------------------------------------------ # bit_rate_hz = 100000 bit_clk_count = self.__axi4_clk_frequency / 100000 bit_clk_delay = int(bit_clk_count / 4) # byte_ctrl = address_bytes * 16 +data_bytes byte_ctrl = 1 * 16 + 1 self.__data_width = 1 # slave_address = 0x50 wr_data = [0x50, byte_ctrl] bit_clk_delay_temp = self.__data_deal.int_2_list(bit_clk_delay, 2) wr_data.extend(bit_clk_delay_temp) self.__axi4lite.write(0x30, wr_data, len(wr_data)) # config edid data------------------------------------------------ edid_720p_data = [ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x10, 0xEC, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x1A, 0x01, 0x03, 0xA1, 0x33, 0x1D, 0x78, 0x0A, 0xEC, 0x18, 0xA3, 0x54, 0x46, 0x98, 0x25, 0x0F, 0x48, 0x4C, 0x21, 0x08, 0x00, 0xB3, 0x00, 0xD1, 0xC0, 0x81, 0x80, 0x81, 0xC0, 0xA9, 0xC0, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00, 0x00, 0xD0, 0x52, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x20, 0x44, 0x69, 0x67, 0x69, 0x6C, 0x65, 0x6E, 0x74, 0x44, 0x56, 0x49, 0x2D, 0x32, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEE ] self._register_write(0, edid_720p_data) self.enable() return None def _register_read(self, address, read_length): read_data = [] for i in range(0, read_length): wr_data = self.__data_deal.int_2_list(address, 2) self.__axi4lite.write(0x38, wr_data, len(wr_data)) rd_data = self.__axi4lite.read(0x3C, 4) read_data_temp = self.__data_deal.list_2_int(rd_data) if (read_data_temp < 0): read_data_temp = read_data_temp + pow(2, 32) read_data_temp = read_data_temp >> 8 * (4 - self.__data_width) read_data.append(read_data_temp) address = address + 1 return read_data def _register_write(self, address, write_data): for i in range(0, len(write_data)): write_data_temp = write_data[i] << 8 * (4 - self.__data_width) wr_data = self.__data_deal.int_2_list(write_data_temp, 4) self.__axi4lite.write(0x34, wr_data, len(wr_data)) wr_data = self.__data_deal.int_2_list(address, 2) self.__axi4lite.write(0x38, wr_data, len(wr_data)) self.__axi4lite.write(0x3A, [0x01], 1) address = address + 1 return None def _axi4_clk_frequency_set(self, clk_frequency): self.__axi4_clk_frequency = clk_frequency
class Axi4Ad717x(object): def __init__(self, name): self.name = name self.reg_num = 8192 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() def enable(self): """Enable this FPGA function""" self.__axi4lite.write(0x10, [0x01], 1) def disable(self): """Disable this FPGA function""" self.__axi4lite.write(0x10, [0x00], 1) def register_read(self, reg_addr): """ Read value from ADC chip register Args: reg_addr: ADC chip register address(0x00-0xff) Returns: register value: (0x00-0xffffffff) """ rd_data = self.__axi4lite.read(0x26, 1) if (rd_data[0] & 0x01 == 0x00): logger.warning('AD717X Bus is busy now') return False com_data = (0x3F & reg_addr) | 0x40 wr_data = [com_data, 0x01] self.__axi4lite.write(0x24, wr_data, len(wr_data)) rd_data = [0x00] timeout_cnt = 0 while (rd_data[0] & 0x01 == 0x00) and (timeout_cnt < 1000): time.sleep(0.001) timeout_cnt = timeout_cnt + 1 rd_data = self.__axi4lite.read(0x26, 1) if (timeout_cnt == 1000): logger.warning('AD717X read register wait timeout') return False rd_data = self.__axi4lite.read(0x28, 4) rd_data = rd_data[0] | (rd_data[1] << 8) | (rd_data[2] << 16) |\ (rd_data[3] << 24) return rd_data def register_write(self, reg_addr, reg_data): """ Write value to ADC chip register Args: reg_addr: ADC chip reg (0x00-0xff) reg_data: register value(0x00-0xffffffff) Returns: True | False """ rd_data = self.__axi4lite.read(0x26, 1) if (rd_data[0] & 0x01 == 0x00): logger.warning('AD717X Bus is busy now') return False wr_data = self.__data_deal.int_2_list(reg_data, 4) com_data = (0x3F & reg_addr) wr_data.append(com_data) wr_data.append(0x01) self.__axi4lite.write(0x20, wr_data, len(wr_data)) rd_data = [0x00] timeout_cnt = 0 while (rd_data[0] & 0x01 == 0x00) and (timeout_cnt < 1000): time.sleep(0.001) rd_data = self.__axi4lite.read(0x26, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 1000): logger.warning('AD717X write register wait finish timeout') return False return True def single_sample_code_get(self): """ ADC chip single sample Returns: (channel,sample_code) """ rd_data = self.register_read(0x01) wr_data = rd_data & 0xFF0F | 0x0000 self.register_write(0x01, wr_data) rd_data = self.register_read(0x01) if ((rd_data & 0x00F0) != 0): logger.warning("AXI4 AD717X 0x01 ==%s" % (hex(rd_data))) return False wr_data = rd_data & 0xFF0F | 0x0010 self.register_write(0x01, wr_data) reg_data = self.register_read(0x04) rd_data = self.__axi4lite.read(0x26, 1) if (rd_data[0] & 0x08 == 0x08): sample_channel = (reg_data & 0x0000000F) sample_data = (reg_data & (0xFFFFFF00)) >> 8 else: sample_channel = 'Null' sample_data = reg_data & (0x00FFFFFF) #logger.info('channel: ',sample_channel,'rd_data: 0x%08x 0x%06x'%(reg_data,sample_data)) return (sample_channel, sample_data) def code_2_mvolt(self, code, mvref, bits): """ Adc sample code conversion to mVolt Args: code: sample code mvref:(value,unit) bits: ADC sample bits AD7175: 24 or 16 bits AD7177: 32 or 24 bits Returns: volt: (value,uinit) """ volt = code volt -= 0x800000 bits = bits - 1 volt /= 1 << bits volt *= mvref[0] return (volt, mvref[1]) def continue_sample_mode(self): """ ADC chip work in continue sample mode,cpu can not control the bus Returns: True | False """ rd_data = self.register_read(0x01) wr_data = rd_data & 0xFF0F | 0x0000 self.register_write(0x01, wr_data) rd_data = self.register_read(0x02) reg_data = rd_data & 0xFF7F | 0x0080 rd_data = self.__axi4lite.read(0x26, 1) if (rd_data[0] & 0x01 == 0x00): logger.warning('Error: AD717X Bus is busy now') return False wr_data = self.__data_deal.int_2_list(reg_data, 4) com_data = (0x3F & 0x02) wr_data.append(com_data) wr_data.append(0x01) self.__axi4lite.write(0x20, wr_data, len(wr_data)) return True def single_sample_mode(self): """ ADC chip exit continue sample mode,cpu can control the bus """ wr_data = [0x44, 0x01] state = self.__axi4lite.write(0x24, wr_data, len(wr_data)) return state def reset(self): """ Reset ADC chip """ wr_data = [0xFF, 0x01] state = self.__axi4lite.write(0x24, wr_data, len(wr_data)) return state def frame_channel_and_samplerate_set(self, channel_no, samplerate): """ Frame channel number and sample rate set. Only used in continue sample wor mode Args: channel_no: channel number samplerate: ADC sample rate """ wr_data = [0, 0, 0, 0] wr_data[0] = samplerate % 256 wr_data[1] = (samplerate >> 8) % 256 wr_data[2] = (samplerate >> 16) % 256 wr_data[3] = channel_no * 16 state = self.__axi4lite.write(0xF0, wr_data, len(wr_data)) return state def data_analysis(self, data_count): """ Adc sample data analysis Args: data_count(int): sample data count Returns: get_data(list): sample data list """ rd_data = self.__axi4lite.read(0x26, 1) if ((rd_data[0] & 0x04) != 0x04): logger.warning('AD717X is not in continuous sample mode') return False wr_data = self.__data_deal.int_2_list(data_count, 2) self.__axi4lite.write(0x61, wr_data, len(wr_data)) self.__axi4lite.write(0x60, [0x01], 1) rd_data = [0x00] while (rd_data[0] & 0x01 == 0x00): time.sleep(0.001) rd_data = self.__axi4lite.read(0x63, 1) get_data = [] for i in range(0, data_count): #rw_addr = i + 0x1000; rw_addr = i * 4 + 0x1000 rd_data = self.__axi4lite.read(rw_addr, 4) #rd_int = self.__data_deal.list_2_int(rd_data) rd_int = rd_data[0] | (rd_data[1] << 8) | (rd_data[2] << 16) |\ (rd_data[3] << 24) #rd_int = rd_int - 0x8000 get_data.append(rd_int) return get_data def _test_register(self, test_data): wr_data = self.__data_deal.int_2_list(test_data, 4) self.__axi4lite.write(0x00, wr_data, len(wr_data)) rd_data = self.__axi4lite.read(0x00, len(wr_data)) test_out = self.__data_deal.list_2_int(rd_data) if (test_out != test_data): logger.error('Register test failure') return False return True
class Axi4Uart(object): def __init__(self,name): self.name = name self.reg_num = 256 self.__axi4lite=Axi4lite(self.name,self.reg_num) self.__axi4_clk_frequency = 125000000 if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail'%(self.name, self.reg_num)) self.__data_deal = DataOperate() rd_data = self.__axi4lite.read(0x0C,2) self._tx_cache = self.__data_deal.list_2_int(rd_data) def enable(self): """ Enable function """ self.__axi4lite.write(0x10, [0x00], 1) self.__axi4lite.write(0x10, [0x01], 1) return None def disable(self): """ Disable function """ self.__axi4lite.write(0x10, [0x00], 1) return None def config(self,baud_rate=115200,data_bits=8,parity_type='NONE',stop_bits=1, time_insert='NONE'): """ Set uart bus parameter Args: baud_rate(int) : UART baud rate data_bits(int) : Data width 5/6/7/8 parity_type(str) : parity type. "ODD"/"EVNE"/"NONE" stop_bits(float) : stop bit width. 1/1.5/2 time_insert(str) : Insert timestamp Control, "TS"/"NONE" Returns: None """ logger.info("%s set baud_rate: %s ; data_bits: %s; stop_bits : %s ;parity: %s; time_insert: %s;"\ %(self.name, baud_rate, data_bits,stop_bits,parity_type,time_insert)) baud_rate_temp = int(pow(2,32)*baud_rate/self.__axi4_clk_frequency) wr_data = self.__data_deal.int_2_list(baud_rate_temp, 4) self.__axi4lite.write(0x20, wr_data, len(wr_data)) if(parity_type == 'ODD'): parity_data = 0x01 elif(parity_type == 'EVNE'): parity_data = 0x00 else: parity_data = 0x02 if(stop_bits == 1): stop_bits_data = 0x04 elif(stop_bits == 1.5): stop_bits_data = 0x08 else: stop_bits_data = 0x0C data_bits_data = (data_bits-1)<<4 wr_data_temp = parity_data | stop_bits_data | data_bits_data self.__axi4lite.write(0x24, [wr_data_temp], 1) if(time_insert == "TS"): self.__axi4lite.write(0x25, [0x01], 1) else: self.__axi4lite.write(0x25, [0x00], 1) self.__axi4lite.write(0x26, [0x11], 1) return None def write(self,wr_data,block='non-block'): """ uart write access Args: write_data(bytes): uart send bytearray Returns: NONE """ i = len(wr_data) wr_data_index = 0 while(i > 0): rd_data = self.__axi4lite.read(0x35,2) cache_deep = self.__data_deal.list_2_int(rd_data) if(cache_deep > i): send_cnt = i else: send_cnt = cache_deep -3 self.__axi4lite.write_byte_array(0x34, wr_data[wr_data_index:wr_data_index+send_cnt], send_cnt, 8) wr_data_index += send_cnt i -= send_cnt if block is 'block': i = 0 while( i < self._tx_cache): rd_data = self.__axi4lite.read(0x35,2) cache_deep = self.__data_deal.list_2_int(rd_data) sleep(10) return None def read(self): """ uart read access Args: NONE Returns: receive_str(bytes): uart receive bytearray """ rd_data = self.__axi4lite.read(0x31, 2) cache_deep = self.__data_deal.list_2_int(rd_data) if cache_deep != 0: rd_data = self.__axi4lite.read_byte_array(0x30, cache_deep, 8) return rd_data else: return None
class Axi4Ad760x(): def __init__(self, name): self.name = name self.reg_num = 8192 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() def enable(self): """Enable this FPGA function""" self.__axi4lite.write(0x10, [0x01], 1) return None def disable(self): """Disable this FPGA function""" self.__axi4lite.write(0x10, [0x00], 1) return None def ad760x_reset(self): """ad760x reset function""" rd_data = self.__axi4lite.read(0x10, 1) rd_data[0] = rd_data[0] | 0x80 self.__axi4lite.write(0x11, rd_data, 1) time.sleep(0.001) rd_data[0] = rd_data[0] & 0x7F self.__axi4lite.write(0x11, rd_data, 1) return None def ad760x_single_sample(self, os, v_range): """ ad760x single sample Args: os(int): Oversampling set(0~7) v_range(string): adc reference voltage set('5V' or '10V') Returns: voltages(list): [ch0_volt,ch1_volt,...,ch7_volt], unit is V """ # ctrl reg cfg # 0x10 [0]--module_en;[4]--continuous_sample_en # 0x11 [2:0]--os;[3]--v_range;[7]--rst_pin_ctrl rd_data = self.__axi4lite.read(0x10, 2) self.__axi4lite.write(0x10, [0x00], 1) rd_data[0] = 0x01 if (v_range == '10V'): rd_data[1] = (rd_data[1] & 0xF0) | ((1 << 3) | os) else: rd_data[1] = (rd_data[1] & 0xF0) | os self.__axi4lite.write(0x10, rd_data, 2) # start sample self.__axi4lite.write(0x12, [0x01], 1) # query state timeout_cnt = 0 rd_data = self.__axi4lite.read(0x13, 1) while (rd_data[0] == 0x00) and timeout_cnt < 100: time.sleep(0.00001) rd_data = self.__axi4lite.read(0x13, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 100): logger.error('ad760x sample timeout') return False #ch0:0x20-0x23;ch1:0x24-0x27;ch2:0x28-0x2B;ch3:0x2C-0x2Fch4:0x30-0x33;ch5:0x34-0x37;ch6:0x38-0x3B;ch7:0x3C-0x3F voltages = [] volt_reg_addr = 0x20 for i in range(8): rd_data = self.__axi4lite.read(volt_reg_addr, 4) volt_temp = self.__data_deal.list_2_int(rd_data) if (v_range == '10V'): volt_temp = volt_temp / pow(2, 32) * 20 else: volt_temp = volt_temp / pow(2, 32) * 10 volt_reg_addr = volt_reg_addr + 0x04 voltages.append(volt_temp) return voltages def ad760x_continuous_sample(self, os, v_range, sample_rate): """ ad760x_continuous_sample enable, and it must invoking the "disable" function to stop the ad760x_continuous_sample. When this function enable, the "ad760x_single_sample" function can't used. os & sample_rate limit description: os == 0: sample_rate 2000~200000Hz os == 1: sample_rate 2000~100000Hz os == 2: sample_rate 2000~50000Hz os == 3: sample_rate 2000~25000Hz os == 4: sample_rate 2000~12500Hz os == 5: sample_rate 2000~6250Hz os == 6: sample_rate 2000~3125Hz os == 7: invalid, out of commission Args: os(int): Oversampling set(0~7) v_range(string): adc reference voltage set('5V' or '10V') sample_rate(int): sample_rate set, 2000~200000Hz Returns: None """ # ctrl reg cfg # 0x10 [0]--module_en;[4]--continuous_sample_en # 0x11 [2:0]--os;[3]--v_range;[7]--rst_pin_ctrl # 0x14~0x15 [15:0] -- sample_rate rd_data = self.__axi4lite.read(0x10, 2) self.__axi4lite.write(0x10, [0x00], 1) rd_data[0] = 0x11 if (v_range == '10V'): rd_data[1] = (rd_data[1] & 0xF0) | ((1 << 3) | os) else: rd_data[1] = (rd_data[1] & 0xF0) | os self.__axi4lite.write(0x10, rd_data, 2) # cfg sample rate wr_data = self.__data_deal.int_2_list( int((125000000 / sample_rate) - 2), 2) self.__axi4lite.write(0x14, wr_data, 2) # start sample self.__axi4lite.write(0x12, [0x01], 1) # Until use disable function to stop continuous sample mode. return None
class Axi4AidMaster(): def __init__(self, name): self.name = name self.reg_num = 8192 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() def enable(self): """Enable this FPGA function""" self.__axi4lite.write(0x10, [0x01], 1) return None def disable(self): """Disable this FPGA function""" self.__axi4lite.write(0x10, [0x00], 1) return None def aid_switch_on(self): """Release aid bus, allow aid communication""" # 0x11 [0]--vdg_switch; [4]--vdg_poll_en rd_data = self.__axi4lite.read(0x11, 1) rd_data[0] = rd_data[0] & 0xFE self.__axi4lite.write(0x11, rd_data, 1) return None def aid_switch_off(self): """Force the aid bus to be low level, forbade aid communication""" # 0x11 [0]--vdg_switch; [4]--vdg_poll_en rd_data = self.__axi4lite.read(0x11, 1) rd_data[0] = rd_data[0] | 0x01 self.__axi4lite.write(0x11, rd_data, 1) return None def aid_detect_poll_on(self): """enable aid detect poll mode, that is the 70ms loop sends a "74 00 01" request command(otpID)""" # 0x11 [0]--vdg_switch; [4]--vdg_poll_en rd_data = self.__axi4lite.read(0x11, 1) rd_data[0] = rd_data[0] | 0x10 self.__axi4lite.write(0x11, rd_data, 1) return None def aid_detect_poll_off(self): """disable aid detect poll mode""" # 0x11 [0]--vdg_switch; [4]--vdg_poll_en rd_data = self.__axi4lite.read(0x11, 1) rd_data[0] = rd_data[0] & 0xEF self.__axi4lite.write(0x11, rd_data, 1) return None def aid_cmd(self, cmd_req_data): """ signal aid cmd communication Args: cmd_req_data(list): aid request command data(except CRC data),len 1~512 Returns: aid_resp_data(list): aid response command data(include CRC data),len 0~512(len=0 --> no aid response data) """ # ctrl reg cfg # 0x10 [0]--module_en # 0x11 [0]--vdg_switch; [4]--vdg_poll_en # 0x12 [0]--start # 0x13 [0]--state # 0x20~0x21 aid_req_len # 0x22~0x23 aid_resp_len # 0x24~0x27 aid_rece_timeout_cnt # 0x80 wr--wr_req_data; rd--rd_resp_data # wait detect poll over rd_data = self.__axi4lite.read(0x11, 1) vdg_poll_en_flag = (rd_data[0] & 0x10) >> 4 if (vdg_poll_en_flag == 0x01): rd_data[0] = rd_data[0] & 0xEF self.__axi4lite.write(0x11, rd_data, 1) timeout_cnt = 0 rd_data = self.__axi4lite.read(0x13, 1) while (rd_data[0] == 0x00) and timeout_cnt < 1000: time.sleep(0.001) rd_data = self.__axi4lite.read(0x13, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 1000): logger.error('wait poll detct timeout') return False # cfg req len aid_req_len = len(cmd_req_data) wr_data = self.__data_deal.int_2_list(aid_req_len, 2) self.__axi4lite.write(0x20, wr_data, len(wr_data)) # wr cmd_req_data to req_fifo self.__axi4lite.write_array(0x80, cmd_req_data, aid_req_len, 8) # start aid communication self.__axi4lite.write(0x12, [0x01], 1) # query state timeout_cnt = 0 rd_data = self.__axi4lite.read(0x13, 1) while (rd_data[0] == 0x00) and timeout_cnt < 10000: time.sleep(0.001) rd_data = self.__axi4lite.read(0x13, 1) timeout_cnt = timeout_cnt + 1 if (timeout_cnt == 10000): logger.error('aid communication timeout') return False # rece cmd_resp_data len rd_data = self.__axi4lite.read(0x22, 2) resp_len = self.__data_deal.list_2_int(rd_data) # rece cmd_resp_data from resp_fifo aid_resp_data = [] if (resp_len != 0): aid_resp_data = self.__axi4lite.read_array(0x80, resp_len, 8) if (vdg_poll_en_flag == 0x01): rd_data = self.__axi4lite.read(0x11, 1) rd_data[0] = rd_data[0] | 0x10 self.__axi4lite.write(0x11, rd_data, 1) return aid_resp_data
class Axi4L2S: def __init__(self, name): self.name = name self.reg_num = 256 self.__axi4lite = Axi4lite(self.name, self.reg_num) if self.__axi4lite.open() is False: logger.error('open %s device register number %d fail' % (self.name, self.reg_num)) self.__data_deal = DataOperate() rd_data = self.__axi4lite.read(0x0C, 2) self.__tx_width = rd_data[0] self.__rx_width = rd_data[1] def write(self, write_data): """ write access Args: write_data(bytes): write data bytes Returns: NONE """ rd_data = self.__axi4lite.read(0x0C, 1) bits_width = rd_data[0] if (len(write_data) % 4 > 0): logger.error('%s: write data length error' % (self.name)) return False i = int(len(write_data) / bits_width) wr_data_index = 0 while (i > 0): rd_data = self.__axi4lite.read(0x10, 2) cache_deep = self.__data_deal.list_2_int(rd_data) if (cache_deep > i): send_cnt = i else: send_cnt = cache_deep - 3 send_byte_cnt = send_cnt * bits_width #self.__axi4lite.write_byte_array(0x14, write_data[wr_data_index:wr_data_index+send_byte_cnt], send_byte_cnt, bits_width*8) self.__axi4lite.write_array( 0x14, write_data[wr_data_index:wr_data_index + send_byte_cnt], send_byte_cnt, bits_width * 8) wr_data_index += send_byte_cnt i -= send_cnt return None def read(self): """ read access Args: NONE Returns: read_data(bytes): read data bytes """ rd_data = self.__axi4lite.read(0x0D, 1) bits_width = rd_data[0] rd_data = self.__axi4lite.read(0x12, 2) cache_deep = self.__data_deal.list_2_int(rd_data) read_data = [] if cache_deep != 0: read_data = self.__axi4lite.read_byte_array( 0x18, cache_deep * bits_width, bits_width * 8) return read_data else: return None def cache_deep(self): """cache_deep""" cache_data = self.__axi4lite.read(0x12, 2) if cache_data != 0: return False else: return True