def i_rra(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
shift = (size * 8) - 1
res = (e_bits.msb(udst, size) << shift) | (udst>>1)
ures = e_bits.unsigned(res, size)
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, e_bits.lsb(udst))
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, ures)
def i_rra(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
shift = (size * 8) - 1
res = (e_bits.msb(udst, size) << shift) | (udst>>1)
ures = e_bits.unsigned(res, size)
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, e_bits.lsb(udst))
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, ures)
def i_rol(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.msb(val, dstSize)
self.setOperValue(op, 0, (val * 2) + tempCf)
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.lsb(val))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ cf)
else:
self.setFlag(EFLAGS_OF, False)
def i_rol(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.msb(val, dstSize)
self.setOperValue(op, 0, (val * 2) + tempCf)
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.lsb(val))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ cf)
else:
self.setFlag(EFLAGS_OF, False)
def i_ror(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.lsb(val)
self.setOperValue(op, 0, (val / 2) + (tempCf * (2 ** dstSize)))
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.msb(val, dstSize))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
# FIXME: This may be broke...the manual is kinda flaky here
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ (e_bits.msb(val, dstSize) - 1))
else:
self.setFlag(EFLAGS_OF, False)
def i_ror(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.lsb(val)
self.setOperValue(op, 0, (val / 2) + (tempCf * (2 ** dstSize)))
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.msb(val, dstSize))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
# FIXME: This may be broke...the manual is kinda flaky here
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ (e_bits.msb(val, dstSize) - 1))
else:
self.setFlag(EFLAGS_OF, False)