def pos_mode(args):
pytrellis.load_database("../../../database")
cfg = FuzzConfig(job="FINDNETS_R{}C{}".format(args.row, args.col),
family="MachXO2",
device="LCMXO2-1200HC",
ncl="plc2route.ncl",
tiles=[])
cfg.setup()
netdata = isptcl.get_wires_at_position(cfg.ncd_prf, (args.row, args.col))
netnames = [x[0] for x in netdata]
arcs = isptcl.get_arcs_on_wires(cfg.ncd_prf, netnames, False,
defaultdict(lambda: str("mark")))
with open(
"r{}c{}_{}out.txt".format(args.row, args.col,
"a_" if args.a else ""), "w") as fp:
for (k, v) in arcs.items():
print("{}:".format(k), file=fp)
for c in v:
if isinstance(c, isptcl.AmbiguousArc):
print(str(c), file=fp)
else:
if not args.a:
print("{} --> {}".format(c[0], c[1]), file=fp)
fp.flush()
print("", file=fp)
def timing_configs(job, design, density="45"):
# speedgrade, fuzzconfig
return [("6",
FuzzConfig(job + "_6", "ECP5", "LFE5U-{}F".format(density), [],
design, "-s 6")),
("7",
FuzzConfig(job + "_7", "ECP5", "LFE5U-{}F".format(density), [],
design, "-s 7")),
("8",
FuzzConfig(job + "_8", "ECP5", "LFE5U-{}F".format(density), [],
design, "-s 8")),
("8_5G",
FuzzConfig(job + "_8_5G", "ECP5", "LFE5UM5G-{}F".format(density),
[], design, "-s 8"))]
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "gsr.ncl"
nonrouting.fuzz_enum_setting(cfg, "GSR.GSRMODE",
["NONE", "ACTIVE_LOW", "ACTIVE_HIGH"],
lambda x: get_substs(gsrmode=x),
empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "GSR.SYNCMODE",
["NONE", "ASYNC", "SYNC"],
lambda x: get_substs(syncmode=x),
empty_bitfile, False)
for rcfg, rc, prefix in [
(FuzzConfig(job="GSR",
family="ECP5",
device="LFE5U-25F",
ncl="gsr_routing_25k.ncl",
tiles=["MIB_R50C4:EFB0_PICB0"]), "R49C4", "25K_"),
(FuzzConfig(job="GSR",
family="ECP5",
device="LFE5U-45F",
ncl="gsr_routing.ncl",
tiles=["MIB_R71C4:EFB0_PICB0"]), "R70C4", "45K_"),
(FuzzConfig(job="GSR",
family="ECP5",
device="LFE5U-85F",
ncl="gsr_routing_85k.ncl",
tiles=["MIB_R95C4:EFB0_PICB0"]), "R94C4", "85K_"),
]:
rcfg.setup()
interconnect.fuzz_interconnect_with_netnames(
rcfg, ["{}_JGSR_GSR".format(rc), "{}_JCLK_GSR".format(rc)],
bidir=True,
nonlocal_prefix=prefix)
def net_mode(args):
pytrellis.load_database("../../../database")
cfg = FuzzConfig(job="FINDNETS_NETS_{}".format(args.nets[0]),
family="MachXO2",
device="LCMXO2-1200HC",
ncl="plc2route.ncl",
tiles=[])
cfg.setup()
arcs = isptcl.get_arcs_on_wires(cfg.ncd_prf, args.nets, False,
defaultdict(lambda: str("mark")))
with open("{}_out.txt".format(args.nets[0]), "w") as fp:
for (k, v) in arcs.items():
print("{}:".format(k), file=fp)
for c in v:
if isinstance(c, isptcl.AmbiguousArc):
print(str(c), file=fp)
else:
print("{} --> {}".format(c[0], c[1]), file=fp)
fp.flush()
print("", file=fp)
from fuzzconfig import FuzzConfig
import interconnect
import pytrellis
jobs = [
{
"cfg": FuzzConfig(job="LECLK_45K", family="ECP5", device="LFE5U-45F", ncl="emux_45k.ncl",
tiles=["CIB_R34C2:ECLK_L"]),
"prim": 1,
"loc": "R34C0",
"globals": ["R34C40_JLECLK1", "R34C40_JBRGECLK1"],
},
{
"cfg": FuzzConfig(job="RECLK_45K", family="ECP5", device="LFE5U-45F", ncl="emux_45k.ncl",
tiles=["CIB_R34C88:ECLK_R"]),
"prim": 0,
"loc": "R34C90",
"globals": ["R34C40_JRECLK0", "R34C40_JBRGECLK0"],
},
]
def get_sinks(job):
# Get the sinks to fuzz for a given edgemux job
loc = job["loc"]
prim = job["prim"]
sinks = []
sinks.append("{}_JCLK0_ECLKBRIDGECS{}".format(loc, prim))
sinks.append("{}_JCLK1_ECLKBRIDGECS{}".format(loc, prim))
sinks.append("{}_JSEL_ECLKBRIDGECS{}".format(loc, prim))
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("EBR_CORE_R28C26", "EBR0", FuzzConfig(job="EBRMODE0", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C26:MIB_EBR", "CIB_R29C27:EBR_1", "CIB_R29C28:EBR_2"])),
("EBR_CORE_R28C29", "EBR1", FuzzConfig(job="EBRMODE1", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C29:MIB_EBR", "CIB_R29C30:EBR_4", "CIB_R29C31:EBR_5"])),
("EBR_CORE_R28C32", "EBR2", FuzzConfig(job="EBRMODE2", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C32:MIB_EBR", "CIB_R29C33:EBR_7", "CIB_R29C34:EBR_8", "CIB_R29C35:EBR_9", "CIB_R29C36:EBR_10", "CIB_R29C37:SPINE_L0"])),
("EBR_CORE_R28C34", "EBR3", FuzzConfig(job="EBRMODE3", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R29C32:MIB_EBR", "CIB_R29C33:EBR_7", "CIB_R29C34:EBR_8", "CIB_R29C35:EBR_9", "CIB_R29C36:EBR_10", "CIB_R29C37:SPINE_L0"])),
]
# These config sets create a minimum bit change for mode fuzzing
defaults = {
"NONE": "",
"DP16K_MODE": "DP16K_MODE:::DATA_WIDTH_A=X18,DATA_WIDTH_B=X18,INIT_DATA=NO_INIT,WID=0b00000000000:CLKA=0,CLKB=0",
"PDP16K_MODE": "PDP16K_MODE:::DATA_WIDTH_R=X36,DATA_WIDTH_W=X36,INIT_DATA=NO_INIT,WID=0b00000000000:CLKR=0,CLKW=0",
"PDPSC16K_MODE": "PDPSC16K_MODE:::DATA_WIDTH_R=X36,DATA_WIDTH_W=X36,INIT_DATA=NO_INIT,WID=0b00000000000:CLK=0",
"SP16K_MODE": "SP16K_MODE:::DATA_WIDTH=X18,INIT_DATA=NO_INIT,WID=0b00000000000:CLK=0",
"FIFO16K_MODE": "FIFO16K_MODE:::FULLBITS=0b00000000000000,DATA_WIDTH_A=X36,DATA_WIDTH_B=X36 FIFO16K_MODE::::CKA=0,CKB=0"
}
def main():
def per_config(x):
site, ebr, cfg = x
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ebr.v"
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False):
if default_cfg:
from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import nonrouting
import re
configs = [
{
"cfg": FuzzConfig(job="DDRDLLL", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R56C2:DOSCL_P18_V18"]),
"rc": (55, 2),
},
{
"cfg": FuzzConfig(job="DDRDLLR", device="LIFCL-40", sv="../shared/route_40.v",
tiles=["CIB_R54C87:DDR_OSC_R"]),
"rc": (54, 86),
},
]
ignore_tiles = set([
"CIB_R55C{}:CIB".format(i) for i in range(1, 87)
] + [
"CIB_R54C86:CIB_LR",
"CIB_R53C86:CIB_LR",
"CIB_R52C86:CIB_LR",
"CIB_R54C1:CIB_LR",
])
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import fuzzloops
import interconnect
jobs = [
FuzzConfig(job="DCS_45k",
family="ECP5",
device="LFE5U-45F",
ncl="empty.ncl",
tiles=[
"MIB_R10C39:EBR_CMUX_UL", "MIB_R10C40:CMUX_UL_0",
"MIB_R10C41:CMUX_UR_0", "MIB_R10C42:EBR_CMUX_UR",
"MIB_R58C39:EBR_CMUX_LL", "MIB_R58C40:CMUX_LL_0",
"MIB_R58C41:CMUX_LR_0", "MIB_R58C42:EBR_CMUX_LR"
]),
FuzzConfig(job="DCS_25k",
family="ECP5",
device="LFE5U-25F",
ncl="empty_25k.ncl",
tiles=[
"MIB_R13C31:DSP_CMUX_UL", "MIB_R13C31:CMUX_UL_0",
"MIB_R13C32:CMUX_UR_0", "MIB_R13C32:DSP_CMUX_UR",
"MIB_R37C30:EBR_CMUX_LL_25K", "MIB_R37C31:CMUX_LL_0",
"MIB_R37C32:CMUX_LR_0", "MIB_R37C33:EBR_CMUX_LR_25K"
]),
FuzzConfig(job="DCS_85k",
family="ECP5",
device="LFE5U-85F",
ncl="empty_85k.ncl",
from fuzzconfig import FuzzConfig
from interconnect import fuzz_interconnect
import re
configs = [
([(11, 7), (11, 19)], [],
FuzzConfig(job="TAPROUTE",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["TAP_PLC_R11C14:TAP_PLC"])),
([(10, 7), (10, 19)], [],
FuzzConfig(job="TAPROUTECIB",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["TAP_CIB_R10C14:TAP_CIB"])),
([(1, 7), (1, 19)], [],
FuzzConfig(job="TAPROUTECIBT",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["TAP_CIBT_R1C14:TAP_CIBT"])),
([(11, 80)], [],
FuzzConfig(job="TAPROUTE_1S",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["TAP_PLC_1S_R11C74:TAP_PLC_1S"])),
([(10, 80)], [],
FuzzConfig(job="TAPROUTECIB_1S",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["TAP_CIB_1S_R10C74:TAP_CIB_1S"])),
([(1, 80)], [],
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
import libpyprjoxide
import fuzzconfig
cfg = FuzzConfig(job="EMPTY",
device="LIFCL-40",
sv="../shared/empty_40.v",
tiles=[])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
libpyprjoxide.add_always_on_bits(fuzzconfig.db, empty)
if __name__ == "__main__":
main()
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("B", "E11", # PR3A,
FuzzConfig(job="IO1D_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R3C75:SYSIO_B1_DED_15K"])),
("A","F16", # PR13A
FuzzConfig(job="IO1A_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R13C75:SYSIO_B1_0_15K", "CIB_R14C75:SYSIO_B1_1_15K"])),
("B","G15", # PR13B
FuzzConfig(job="IO1B_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R13C75:SYSIO_B1_0_15K", "CIB_R14C75:SYSIO_B1_1_15K"])),
("A","E15", # PT67A
FuzzConfig(job="IO0A_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R0C67:SYSIO_B0_0_15K"])),
("B","E16", # PT67B
FuzzConfig(job="IO0B_17K", device="LIFCL-17", sv="../shared/empty_17.v", tiles=["CIB_R0C67:SYSIO_B0_0_15K"])),
("A","F16", # PR8A
FuzzConfig(job="IO1AO", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R8C87:SYSIO_B1_0_ODD"])),
("B","F17", # PR8B
FuzzConfig(job="IO1BO", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R8C87:SYSIO_B1_0_ODD"])),
("A","F14", # PR6A
FuzzConfig(job="IO1AE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R6C87:SYSIO_B1_0_EVEN"])),
("B","F15", # PR6B
FuzzConfig(job="IO1BE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R6C87:SYSIO_B1_0_EVEN"])),
("A","F18", # PR10A
FuzzConfig(job="IC1A", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R10C87:SYSIO_B1_0_C", "CIB_R11C87:SYSIO_B1_0_REM"])),
("B","F19", # PR10B
FuzzConfig(job="IC1B", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R10C87:SYSIO_B1_0_C", "CIB_R11C87:SYSIO_B1_0_REM"])),
("A","N14", # PR24A
FuzzConfig(job="IO2AE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R24C87:SYSIO_B2_0_EVEN"])),
glb_ids))
# Phantom DCCs- First fill in "T"/"B", and then global id
ud_nets.extend(net_product(
net_product([rc_prefix + "CLKI{{}}{}_DCC",
# rc_prefix + "JCE{{}}{}_DCC", # TODO: These nets may not exist?
rc_prefix + "CLKO{{}}{}_DCC"], ("T", "B")),
glb_ids))
return ud_nets
def flatten_nets(tilepos):
return [nets for netpair in [(0, 4), (1, 5), (2, 6), (3, 7)] for nets in mk_nets(tilepos, netpair)]
jobs = [
(FuzzConfig(job="GLB_UPDOWN26", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C4:CIB_EBR0"]), mk_nets((6, 4), (2, 6))),
(FuzzConfig(job="GLB_UPDOWN15", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C7:CIB_EBR0"]), mk_nets((6, 7), (1, 5))),
(FuzzConfig(job="GLB_UPDOWN04", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C10:CIB_EBR0"]), mk_nets((6, 10), (0, 4))),
(FuzzConfig(job="GLB_UPDOWN37", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C17:CIB_EBR0"]), mk_nets((6, 17), (3, 7))),
(FuzzConfig(job="CIB0_EBR0_END0_UPDOWN", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C1:CIB_EBR0_END0"]), flatten_nets((6,1))),
(FuzzConfig(job="CIB0_EBR2_END0_UPDOWN", family="MachXO2", device="LCMXO2-1200HC", ncl="tap.ncl",
tiles=["CIB_R6C22:CIB_EBR2_END0"]), flatten_nets((6,22)))
]
def main(args):
pytrellis.load_database("../../../database")
from fuzzconfig import FuzzConfig
import nonrouting
from interconnect import fuzz_interconnect
import lapie
import re
import fuzzloops
configs = [
((46, 6),
FuzzConfig(job="CIBENABLE",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["CIB_R46C6:CIB"])),
((1, 18),
FuzzConfig(job="CIBTENABLE",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["CIB_R1C18:CIB_T"])),
((23, 86),
FuzzConfig(job="CIBLRENABLE",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["CIB_R23C86:CIB_LR"])),
((37, 86),
FuzzConfig(job="CIBLRAENABLE",
device="LIFCL-40",
sv="../shared/route_40.v",
tiles=["CIB_R37C86:CIB_LR_A", "CIB_R38C86:CIB_LR_B"])),
]
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import nets
import pytrellis
import re
# No evidence this affects any bits.
cfg = FuzzConfig(job="PLC2MKMUX",
family="MachXO2",
device="LCMXO2-1200HC",
ncl="empty.ncl",
tiles=["R10C11:PLC"])
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "mkmux.ncl"
def per_slice(slicen):
def get_substs(m0mux="M0", m1mux="M1", f_mode="F"):
if m0mux == "OFF":
s_m0mux = "#OFF"
else:
s_m0mux = m0mux
return dict(slice=slicen, m0mux=s_m0mux, m1mux=m1mux)
nonrouting.fuzz_enum_setting(cfg, "SLICE{}.M0MUX".format(slicen),
from fuzzconfig import FuzzConfig
import interconnect
import pytrellis
jobs = [
{
"cfg":
FuzzConfig(job="LMID_45K",
family="ECP5",
device="LFE5U-45F",
ncl="emux_45k.ncl",
tiles=["MIB_R34C3:LMID_0"]),
"mux_output":
"R34C21_HPFE{:02d}00",
"dcc_loc":
"R34C1",
"dcc_pos":
"L",
"size":
14,
"prefix":
"45K_",
"cibclk": [
"R34C1_JLLQPCLKCIB1", "R34C1_JLLQPCLKCIB0", "R34C1_JLLMPCLKCIB0",
"R34C1_JULQPCLKCIB0", "R34C1_JULQPCLKCIB1", "R34C1_JULMPCLKCIB0"
]
},
{
"cfg":
FuzzConfig(job="RMID_45K",
family="ECP5",
from fuzzconfig import FuzzConfig
import interconnect
import nets
import pytrellis
import re
jobs = [{
"pos": [(47, 0), (48, 0), (49, 0)],
"cfg":
FuzzConfig(job="PIOROUTEL",
family="ECP5",
device="LFE5U-45F",
ncl="pioroute.ncl",
tiles=["MIB_R47C0:PICL0", "MIB_R48C0:PICL1", "MIB_R49C0:PICL2"])
}, {
"pos": [(47, 90), (48, 90), (49, 90)],
"cfg":
FuzzConfig(
job="PIOROUTER",
family="ECP5",
device="LFE5U-45F",
ncl="pioroute.ncl",
tiles=["MIB_R47C90:PICR0", "MIB_R48C90:PICR1", "MIB_R49C90:PICR2"])
}, {
"pos": [(0, 22), (1, 23), (0, 22), (1, 23)],
"cfg":
FuzzConfig(job="PIOROUTET",
family="ECP5",
device="LFE5U-45F",
ncl="pioroute.ncl",
tiles=[
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
from interconnect import fuzz_interconnect
cfg = FuzzConfig(job="OSCMODE", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R0C77:EFB_1_OSC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "osc.v"
def bin_to_int(x):
val = 0
mul = 1
for bit in x:
if bit:
val |= mul
mul *= 2
return val
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
from fuzzconfig import FuzzConfig
import nonrouting
import nets
import pytrellis
import re
import fuzzloops
jobs = [
{
"cfg": FuzzConfig(job="PIOL", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R59C0:PICL0", "MIB_R60C0:PICL1", "MIB_R61C0:PICL2"]),
"side": "L",
"pins": [("M4", "A"), ("N5", "B"), ("N4", "C"), ("P5", "D")]
},
{
"cfg": FuzzConfig(job="PIOL_CLR", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R20C0:PICL0", "MIB_R21C0:PICL1", "MIB_R22C0:MIB_CIB_LR",
"MIB_R22C0:MIB_CIB_LRC"]),
"side": "L",
"pins": [("F4", "A"), ("E3", "B"), ("E5", "C"), ("F5", "D")]
},
{
"cfg": FuzzConfig(job="PIOL_DQS01", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1_DQS0", "MIB_R16C0:PICL2_DQS1"]),
"side": "L",
"pins": [("C4", "A"), ("B4", "B"), ("A3", "C"), ("B3", "D")]
},
{
"cfg": FuzzConfig(job="PIOL_DQS23", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R17C0:PICL0_DQS2", "MIB_R18C0:PICL1_DQS3", "MIB_R19C0:PICL2"]),
"side": "L",
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import fuzzloops
jobs = [
("R25C22", "EBR0", FuzzConfig(job="EBROUTE0", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
tiles=["MIB_R25C22:MIB_EBR0", "MIB_R25C23:MIB_EBR1"])),
("R25C24", "EBR1", FuzzConfig(job="EBROUTE1", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
tiles=["MIB_R25C24:MIB_EBR2", "MIB_R25C25:MIB_EBR3", "MIB_R25C26:MIB_EBR4"])),
("R25C26", "EBR2", FuzzConfig(job="EBROUTE2", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
tiles=["MIB_R25C26:MIB_EBR4", "MIB_R25C27:MIB_EBR5", "MIB_R25C28:MIB_EBR6"])),
("R25C28", "EBR3", FuzzConfig(job="EBROUTE3", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
tiles=["MIB_R25C28:MIB_EBR6", "MIB_R25C29:MIB_EBR7", "MIB_R25C30:MIB_EBR8"])),
]
def main():
pytrellis.load_database("../../../database")
def per_job(job):
def get_substs(mode, settings):
ebrloc = loc
if mode == "NONE":
# easier to move EBR out the way than remove it
ebrloc = "R25C60"
mode = "PDPW16KD"
if mode == "PDPW16KD" and "DATA_WIDTH_R" not in settings:
settings["DATA_WIDTH_R"] = "18"
if mode == "PDPW16KD" and "DATA_WIDTH_W" not in settings:
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import nets
import pytrellis
import re
cfg = FuzzConfig(job="PLC2INIT",
family="ECP5",
device="LFE5U-25F",
ncl="empty.ncl",
tiles=["R19C33:PLC2"])
def get_lut_function(init_bits):
sop_terms = []
lut_inputs = ["A", "B", "C", "D"]
for i in range(16):
if init_bits[i]:
p_terms = []
for j in range(4):
if i & (1 << j) != 0:
p_terms.append(lut_inputs[j])
else:
p_terms.append("~" + lut_inputs[j])
sop_terms.append("({})".format("*".join(p_terms)))
if len(sop_terms) == 0:
lut_func = "0"
else:
lut_func = "+".join(sop_terms)
return lut_func
from fuzzconfig import FuzzConfig
import interconnect
import nets
import pytrellis
import re
cfg = FuzzConfig(job="CIBROUTE",
family="ECP5",
device="LFE5U-25F",
ncl="cibroute.ncl",
tiles=["CIB_R1C16:CIB"])
def main():
pytrellis.load_database("../../database")
cfg.setup()
span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}')
def nn_filter(net, netnames):
""" Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally
left out by Tcl"""
return ((net in netnames or span1_re.match(net))
and nets.is_cib(net)) or nets.is_global(net)
def fc_filter(arc, netnames):
""" Ignore connections between two general routing nets. These are edge buffers which vary based on location
and must be excluded from the CIB database.
"""
return not (nets.general_routing_re.match(arc[0])
and nets.general_routing_re.match(arc[1]))
"MIB_R13C21:MIB_DSP8",
"MIB_R13C21:MIB2_DSP8",
]
def get_tiles(first):
#
# Get the list of tiles, placing a certain tile first so it is prioritised for fixed conns
return [first] + [_ for _ in dsp_tiles if _ != first]
jobs = [
((13, 13),
FuzzConfig(job="DSPROUTE0",
family="ECP5",
device="LFE5U-25F",
ncl="dsproute.ncl",
tiles=get_tiles("MIB_R13C13:MIB_DSP0"))),
((13, 14),
FuzzConfig(job="DSPROUTE1",
family="ECP5",
device="LFE5U-25F",
ncl="dsproute.ncl",
tiles=get_tiles("MIB_R13C14:MIB_DSP1"))),
((13, 15),
FuzzConfig(job="DSPROUTE1",
family="ECP5",
device="LFE5U-25F",
ncl="dsproute.ncl",
tiles=get_tiles("MIB_R13C15:MIB_DSP2"))),
]
from fuzzconfig import FuzzConfig
import interconnect
import nets
import pytrellis
import re
import argparse
import fuzzloops
import nonrouting
import os
jobs = [
{
"cfg":
FuzzConfig(job="PICB0_AB",
family="MachXO2",
device="LCMXO2-1200HC",
ncl="empty.ncl",
tiles=["PB11:PIC_B0"]),
"side":
"B",
"pins": [("13", "A"), ("14", "B")]
},
# Split into multiple jobs, because Diamond chokes if the I/Os don't
# actually physically exist (QFN32 is default).
{
"cfg":
FuzzConfig(job="PICB0_CD",
family="MachXO2",
device="LCMXO2-1200HC",
ncl="empty.ncl",
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
{
"cfg": FuzzConfig(job="ECLK0", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C48:ECLK_0", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C50:BMID_1_ECLK_2", "CIB_R56C51:ECLK_3"]),
"rc": (55, 48),
"bank": 5,
},
{
"cfg": FuzzConfig(job="ECLK1", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C48:ECLK_0", "CIB_R56C50:BMID_1_ECLK_2", "CIB_R56C51:ECLK_3"]),
"rc": (55, 49),
"bank": 4,
},
{
"cfg": FuzzConfig(job="ECLK2", device="LIFCL-40", sv="../shared/empty_40.v", tiles=["CIB_R56C50:BMID_1_ECLK_2", "CIB_R56C49:BMID_0_ECLK_1", "CIB_R56C48:ECLK_0", "CIB_R56C51:ECLK_3"]),
"rc": (55, 50),
"bank": 3,
},
]
def per_loc(x):
cfg = x["cfg"]
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "eclkprim.v"
r, c = x["rc"]
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import fuzzloops
import interconnect
import os
cfg = FuzzConfig(job="BITARGS", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R71C4:EFB0_PICB0", "MIB_R71C5:EFB1_PICB1", "MIB_R71C6:EFB2_PICB0",
"MIB_R71C7:EFB3_PICB1", "MIB_R71C3:BANKREF8"])
def get_substs(config):
os.environ["BITARGS"] = " ".join(["-g {}:{}".format(k, v) for k, v in config.items()])
return {}
def main():
pytrellis.load_database("../../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.DONEPHASE", ["T0", "T1", "T2", "T3"],
lambda x: get_substs(dict(DONEPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GOEPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GOEPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GSRPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GSRPHASE=x)), empty_bitfile, False)
nonrouting.fuzz_enum_setting(cfg, "SYSCONFIG.GWEPHASE", ["T1", "T2", "T3"],
lambda x: get_substs(dict(GWEPHASE=x)), empty_bitfile, False)
if __name__ == "__main__":
main()
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import fuzzloops
jobs = [
{
"cfg":
FuzzConfig(
job="IOLOGICLA",
family="ECP5",
device="LFE5U-25F",
ncl="empty.ncl",
tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
"side":
"L",
"site":
"IOL_L14A",
"iol":
"A",
"rc":
"R14C0",
},
{
"cfg":
FuzzConfig(
job="IOLOGICLB",
family="ECP5",
device="LFE5U-25F",
ncl="empty.ncl",
tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
configs = [
("LRAM_CORE_R18C86", "LRAM0",
FuzzConfig(job="LRAM0",
device="LIFCL-40",
sv="../shared/empty_40.v",
tiles=["CIB_R23C87:LRAM_0"])),
("LRAM_CORE_R40C86", "LRAM1",
FuzzConfig(job="LRAM1",
device="LIFCL-40",
sv="../shared/empty_40.v",
tiles=[
"CIB_R41C87:LRAM_1",
])),
]
def main():
def per_config(x):
site, lram, cfg = x
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "lram.v"
def get_substs(mode="NONE", kv=None, mux=False):
if kv is None:
config = ""
(which are named as LUT inputs [A-D][0-7]). So this horrible hack emerges instead, whereby we trace the CIB->EBR
interconnect and drive constants on the EBR instead. We can't treat this as just an EBR configuration as it applies to
all CIBs, including those where this would be difficult to fuzz and location-dependant. So there's probably not much
choice...
"""
# List of all pins to fuzz
fuzz_pins = [
"JA0", "JA1", "JA2", "JA3", "JA4", "JA5", "JA6", "JA7",
"JB0", "JB1", "JB2", "JB3", "JB4", "JB5", "JB6", "JB7",
"JC0", "JC1", "JC2", "JC3", "JC4", "JC5", "JC6", "JC7",
"JD0", "JD1", "JD2", "JD3", "JD4", "JD5", "JD6", "JD7",
"JCE0", "JCE1", "JCE2", "JCE3", "JCLK0", "JCLK1", "JLSR0", "JLSR1"
]
cfg = FuzzConfig(job="CIBCONST", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
tiles=["CIB_R25C26:CIB_EBR", "CIB_R25C27:CIB_EBR", "CIB_R25C28:CIB_EBR"])
def main():
pytrellis.load_database("../../database")
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "cibconst.ncl"
def per_pin(pin):
def get_substs(sig, val):
if val == pin:
val = "#SIG"
subs = {"sig": sig, "val": val}
return subs
from fuzzconfig import FuzzConfig
import nonrouting
import fuzzloops
import re
cfg = FuzzConfig(job="REGCFG",
device="LIFCL-40",
sv="../shared/empty_40.v",
tiles=["R2C2:PLC"])
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ff.v"
def per_slice(slicen):
for r in range(2):
def get_substs(regset="SET",
sel="DL",
lsrmode="LSR",
srmode="LSR_OVER_CE",
gsr="DISABLED",
mux="",
used="",
arc=""):
return dict(z=slicen,
k=str(r),
mux=mux,
regset=regset,
from fuzzconfig import FuzzConfig
import nonrouting
import nets
import pytrellis
import re
import fuzzloops
jobs = [
{
"cfg": FuzzConfig(job="PIOL", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R59C0:PICL0", "MIB_R60C0:PICL1", "MIB_R61C0:PICL2"]),
"side": "L",
"pins": [("M4", "A"), ("N5", "B"), ("N4", "C"), ("P5", "D")]
},
{
"cfg": FuzzConfig(job="PIOR", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
tiles=["MIB_R35C90:PICR0", "MIB_R36C90:PICR1", "MIB_R37C90:PICR2"]),
"side": "R",
"pins": [("L20", "A"), ("M20", "B"), ("L19", "C"), ("M19", "D")]
},
]
def main():
pytrellis.load_database("../../../database")
for job in jobs:
cfg = job["cfg"]
side = job["side"]
