Example #1
0
def test_no_jump_zero_with_non_zero():
    network = core.Network()
    clock = gates.Switch(network)
    write_flag = gates.Switch(network)
    address = test_utils.BinaryIn(network, 2)
    data_in = test_utils.BinaryIn(network, 8)
    jump_out, pc_in, pc_write = jump.jump(clock, write_flag, address, data_in)
    jump_out = test_utils.BinaryOut(jump_out)
    pc_in = test_utils.BinaryOut(pc_in)
    network.drain()

    data_in.write(212)
    address.write(1)
    write_flag.write(1)
    network.drain()
    assert not pc_write.read()

    clock.write(1)
    network.drain()
    assert not pc_write.read()

    clock.write(0)
    network.drain()
    assert not pc_write.read()
    write_flag.write(0)

    data_in.write(1)
    address.write(2)
    network.drain()
    assert not pc_write.read()

    write_flag.write(1)
    network.drain()
    assert not pc_write.read()
Example #2
0
def test_jump():
    network = core.Network()
    clock = gates.Switch(network)
    write_flag = gates.Switch(network)
    address = test_utils.BinaryIn(network, 2)
    data_in = test_utils.BinaryIn(network, 8)
    jump_out, pc_in, pc_write = jump.jump(clock, write_flag, address, data_in)
    jump_out = test_utils.BinaryOut(jump_out)
    pc_in = test_utils.BinaryOut(pc_in)
    network.drain()

    data_in.write(123)
    address.write(0)
    network.drain()
    assert not pc_write.read()

    write_flag.write(True)
    network.drain()
    assert pc_in.read() == 123
    assert pc_write.read()

    write_flag.write(False)
    network.drain()
    assert not pc_write.read()
Example #3
0
def computer(clock, rom_content):
    network = clock.network

    # cpu
    data_in = PlaceholderWord(network, WORD_SIZE)
    pc_in = PlaceholderWord(network, WORD_SIZE)
    pc_write = Placeholder(network)
    address, data_out, write_out = cpu_core.cpu_core(clock, data_in, pc_in,
                                                     pc_write)

    # rom
    rom_write = Placeholder(network)
    rom_data = memory.rom(clock, rom_write, address, data_out, ROM_SIZE,
                          rom_content)
    rom_module = Module('rom', ROM_BASE, ROM_SIZE, rom_data, rom_write)

    # add
    add_write = Placeholder(network)
    add_data = math.add(clock, add_write, address, data_out)
    add_module = Module('add', ADD_BASE, 2, add_data, add_write)

    # sub
    sub_write = Placeholder(network)
    sub_data = math.sub(clock, sub_write, address, data_out)
    sub_module = Module('sub', SUB_BASE, 2, sub_data, sub_write)

    # mult
    mult_write = Placeholder(network)
    mult_data = math.mult(clock, mult_write, address, data_out)
    mult_module = Module('mult', MULT_BASE, 2, mult_data, mult_write)

    # shift right
    shr_write = Placeholder(network)
    shr_data = math.shift_right(clock, shr_write, address, data_out)
    shr_module = Module('shr', SHR_BASE, 2, shr_data, shr_write)

    # lit
    low_literal_write = Placeholder(network)
    low_literal_data = literals.low_literal(clock, low_literal_write, address,
                                            data_out, LIT_SIZE)
    low_literal_module = Module('lit', LIT_BASE, LIT_SIZE, low_literal_data,
                                low_literal_write)

    # print
    print_write = Placeholder(network)
    print_data = memory.memory(clock, print_write, address, data_out, 0)
    print_module = Module('print', PRINT_BASE, 0, print_data, print_write)

    # ram
    ram_write = Placeholder(network)
    ram_data = memory.memory(clock, ram_write, address, data_out, RAM_SIZE)
    ram_module = Module('ram', RAM_BASE, RAM_SIZE, ram_data, ram_write)

    # jump
    jump_write = Placeholder(network)
    jump_data, _pc_in, _pc_write = jump.jump(clock, jump_write, address,
                                             data_out)
    pc_in.replace(_pc_in)
    pc_write.replace(_pc_write)
    jump_module = Module('jump', JUMP_BASE, 2, jump_data, jump_write)

    modules = [
        rom_module,
        low_literal_module,
        ram_module,
        add_module,
        sub_module,
        mult_module,
        jump_module,
        print_module,
        shr_module,
    ]

    # bus ties it all together
    module_data_lines = [(m.base_address, m.address_size, m.data_lines)
                         for m in modules]
    data_from_bus, write_lines = bus.bus(address, write_out, module_data_lines)
    data_in.replace(data_from_bus)
    for write_line, module in zip(write_lines, modules):
        module.write_line.replace(write_line)

    # print out the module sizes
    print('cpu', data_out[0].block.size)
    for module in modules:
        print(module.name, module.data_lines[0].block.size)
    print('bus', data_from_bus[0].block.size)
    print('total', network.get_size())

    return print_write, print_data