def ExportHierIla(): archive_dir = './archive' if not os.path.exists(archive_dir): os.makedirs(archive_dir) gb = GBArch() defUSts(gb) defNext(gb) rdDefNext(gb) setNext(gb) gb.exportModel(archive_dir + '/gb_high.abst')
def createILA(): gb = GBArch() U1(gb) U2(gb) U3(gb) U4(gb) WRI(gb) gb.setNext() verilogFile = 'gb_verilog_wri.v' gb.exportVerilog(verilogFile)
def createILA(): gb = GBArch() U1(gb) U1b(gb) U2(gb) U3(gb) U3b(gb) U4(gb) RDI(gb) U1c(gb) gb.setNext() verilogFile = 'gb_verilog_rdi.v' gb.exportVerilog(verilogFile)
arg_0_TDATA_nxt = gb.arg_0_TDATA gb.arg_0_TDATA_nxt = ila.ite(decode, arg_0_TDATA_nxt, gb.arg_0_TDATA_nxt) gbit_nxt = ila.ite((gb.RAM_x == gb.RAM_x_M) & (gb.RAM_y == gb.RAM_y_M), gb.gbit + 1, gb.gbit) gb.gbit_nxt = ila.ite(decode, gbit_nxt, gb.gbit_nxt) # other states are not affected gb.cur_pix_nxt = ila.ite(decode, gb.cur_pix, gb.cur_pix_nxt) gb.RAM_x_nxt = ila.ite(decode, gb.RAM_x, gb.RAM_x_nxt) gb.RAM_y_nxt = ila.ite(decode, gb.RAM_y, gb.RAM_y_nxt) gb.RAM_w_nxt = ila.ite(decode, gb.RAM_w, gb.RAM_w_nxt) for i in xrange(0, gb.RAM_size): gb.RAM_nxt[i] = ila.ite(decode, gb.RAM[i], gb.RAM_nxt[i]) for i in xrange(0, gb.stencil_size): gb.stencil_nxt[i] = ila.ite(decode, gb.stencil[i], gb.stencil_nxt[i]) def setNext(gb): gb.setNext() if __name__ == '__main__': gb = GBArch() defNext(gb) setNext(gb) verilogFile = 'gb_verilog_rdi.v' gb.exportVerilog(verilogFile)
gb.stencil_stream_empty_nxt) # stencil_stream_buff for i in xrange(0, gb.stencil_stream_size): stencil_stream_buff_nxt = gb.stencil_stream_buff[i] gb.stencil_stream_buff_nxt[i] = ila.ite(decode, stencil_stream_buff_nxt, gb.stencil_stream_buff_nxt[i]) # gb_p_cnt gb_p_cnt_nxt = gb.gb_p_cnt gb.gb_p_cnt_nxt = ila.ite(decode, gb_p_cnt_nxt, gb.gb_p_cnt_nxt) # gb_pp_it for i in xrange(0, gb.gb_pp_size): gb_pp_it_i_nxt = gb.gb_pp_it[i] gb.gb_pp_it_nxt[i] = ila.ite(decode, gb_pp_it_i_nxt, gb.gb_pp_it_nxt[i]) # gb_exit_it for i in xrange(0, gb.gb_exit_size): gb_exit_it_i_nxt = gb.gb_exit_it[i] gb.gb_exit_it_nxt[i] = ila.ite(decode, gb_exit_it_i_nxt, gb.gb_exit_it_nxt[i]) if __name__ == '__main__': m = GBArch() WRI(m) print 'add write instruction'
WRU0(gb) WRU1(gb) # Connect next state function to the abstraction def setNext(gb): gb.setNext() m = gb.abst m.set_next('proc_in', gb.proc_in_nxt) m.set_next('pre_pix', gb.pre_pix_nxt) m.set_next('st_ready', gb.st_ready_nxt) if __name__ == '__main__': gb = GBArch() defUSts(gb) defNext(gb) rdDefNext(gb) setNext(gb) def ExportHierIla(): archive_dir = './archive' if not os.path.exists(archive_dir): os.makedirs(archive_dir) gb = GBArch()
def ExportHierIla(): archive_dir = './archive' if not os.path.exists(archive_dir): os.makedirs(archive_dir) gb_top = GBArch() WRI(gb_top) RDI(gb_top) gb_top.setNext() gb_top.setDecode() gb_top.exportModel(archive_dir + '/gb_top.ila') gb_child = GBArch() U1(gb_child) U2(gb_child) U3(gb_child) U4(gb_child) gb_child.setNext() gb_child.setDecode() gb_child.exportModel(archive_dir + '/gb_child.ila')