def incorporate_cache(self, board: AbstractBoard) -> None:
requires(coherence_protocol_required=CoherenceProtocol.CHI)
self.ruby_system = RubySystem()
# Ruby's global network.
self.ruby_system.network = SimplePt2Pt(self.ruby_system)
# Network configurations
# virtual networks: 0=request, 1=snoop, 2=response, 3=data
self.ruby_system.number_of_virtual_networks = 4
self.ruby_system.network.number_of_virtual_networks = 4
# Create a single centralized directory
self.directory = SimpleDirectory(
self.ruby_system.network,
cache_line_size=board.get_cache_line_size(),
clk_domain=board.get_clock_domain(),
)
self.directory.ruby_system = self.ruby_system
# Create one core cluster with a split I/D cache for each core
self.core_clusters = [
self._create_core_cluster(core, i, board)
for i, core in enumerate(board.get_processor().get_cores())
]
# Create the coherent side of the memory controllers
self.memory_controllers = self._create_memory_controllers(board)
self.directory.downstream_destinations = self.memory_controllers
# Create the DMA Controllers, if required.
if board.has_dma_ports():
self.dma_controllers = self._create_dma_controllers(board)
self.ruby_system.num_of_sequencers = len(self.core_clusters) * 2 \
+ len(self.dma_controllers)
else:
self.ruby_system.num_of_sequencers = len(self.core_clusters) * 2
self.ruby_system.network.connectControllers(
list(
chain.from_iterable( # Grab the controllers from each cluster
[(cluster.dcache, cluster.icache)
for cluster in self.core_clusters])) +
self.memory_controllers + [self.directory] +
(self.dma_controllers if board.has_dma_ports() else []))
self.ruby_system.network.setup_buffers()
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.ruby_system.sys_port_proxy = RubyPortProxy()
board.connect_system_port(self.ruby_system.sys_port_proxy.in_ports)
"--resource-directory",
type=str,
required=False,
help="The directory in which resources will be downloaded or exist.",
)
args = parser.parse_args()
coherence_protocol_required = None
if args.mem_system == "mi_example":
coherence_protocol_required = CoherenceProtocol.MI_EXAMPLE
elif args.mem_system == "mesi_two_level":
coherence_protocol_required = CoherenceProtocol.MESI_TWO_LEVEL
requires(isa_required=ISA.X86,
coherence_protocol_required=coherence_protocol_required,
kvm_required=(args.cpu == "kvm"))
cache_hierarchy = None
if args.mem_system == "mi_example":
from gem5.components.cachehierarchies.ruby.\
mi_example_cache_hierarchy import (
MIExampleCacheHierarchy,
)
cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
elif args.mem_system == "mesi_two_level":
from gem5.components.cachehierarchies.ruby.\
mesi_two_level_cache_hierarchy import (
MESITwoLevelCacheHierarchy,
)
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor, )
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.coherence_protocol import CoherenceProtocol
from gem5.resources.resource import Resource, CustomDiskImageResource
from m5.stats.gem5stats import get_simstat
from m5.util import warn
from m5.util import fatal
# We check for the required gem5 build.
requires(
isa_required=ISA.X86,
coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
kvm_required=True,
)
# Following are the list of benchmark programs for SPEC CPU2006.
# Note that 400.perlbench, 447.dealII, 450.soplex and 483.xalancbmk
# have build errors, and, therefore cannot be executed. More information is
# available at: https://www.gem5.org/documentation/benchmark_status/gem5-20
benchmark_choices = [
'400.perlbench', '401.bzip2', '403.gcc', '410.bwaves', '416.gamess',
'429.mcf', '433.milc', '435.gromacs', '436.cactusADM', '437.leslie3d',
'444.namd', '445.gobmk', '447.dealII', '450.soplex', '453.povray',
'454.calculix', '456.hmmer', '458.sjeng', '459.GemsFDTD', '462.libquantum',
'464.h264ref', '465.tonto', '470.lbm', '471.omnetpp', '473.astar',
'481.wrf', '482.sphinx3', '483.xalancbmk', '998.specrand', '999.specrand'
args = parse_options()
cpu = None
if args.cpu_type == "atomic":
cpu = CPUTypes.ATOMIC
elif args.cpu_type == "timing":
cpu = CPUTypes.TIMING
elif args.cpu_type == "o3":
cpu = CPUTypes.O3
else:
assert (False, "The CPU type must be one of: {atomic, timing, o3}")
bbl = CustomResource(
args.bbl) if args.bbl else Resource('riscv-boot-exit-nodisk')
# Run a check to ensure the right version of gem5 is being used.
requires(isa_required=ISA.RISCV)
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy \
import (
PrivateL1PrivateL2CacheHierarchy,
)
# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(l1d_size="32KiB",
l1i_size="32KiB",
l2_size="512KiB")
# Setup the system memory.
memory = SingleChannelDDR3_1600()
# Setup a single core Processor.
from gem5.resources.resource import Resource
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor, )
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa, get_runtime_coherence_protocol
from gem5.simulate.simulator import Simulator
from gem5.simulate.exit_event import ExitEvent
from gem5.utils.requires import requires
import time
import argparse
requires(isa_required=ISA.X86)
parser = argparse.ArgumentParser(
description="A script to run the PARSEC benchmarks on a basic X86 full "
"system.")
parser.add_argument(
"-n",
"--num-cpus",
type=int,
choices=(1, 2, 8),
required=True,
help="The number of CPUs. Note: 1, 2, and 8 cores supported on KVM; 1 and "
"2 supported on TimingSimpleCPU.",
)
```
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
# This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
# an exception will be thrown.
requires(isa_required=ISA.ARM)
# In this setup we don't have a cache. `NoCache` can be used for such setups.
cache_hierarchy = NoCache()
# We use a single channel DDR3_1600 memory system
memory = SingleChannelDDR3_1600(size="32MB")
# We use a simple Timing processor with one core.
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
# The gem5 library simble board which can be used to run simple SE-mode
# simulations.
board = SimpleBoard(
clk_freq="3GHz",
processor=processor,