Example #1
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "ngspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram
        import setup_hold

        sh = setup_hold.setup_hold()
        [one_setup_time, zero_setup_time] = sh.hold_time()

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        globals.set_spice()

        if OPTS.tech_name == "freepdk45":
            self.assertTrue(isclose(one_setup_time, -0.0048828125))
            self.assertTrue(isclose(zero_setup_time, -0.010986328125))
        elif OPTS.tech_name == "scn3me_subm":
            self.assertTrue(isclose(one_setup_time,
                                    0.45654296875))  # diff than hspice
            self.assertTrue(isclose(zero_setup_time, -0.0830078125))
        else:
            self.assertTrue(False)  # other techs fail
Example #2
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))

        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "hspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram
        import setup_hold

        sh = setup_hold.setup_hold()
        [one_setup_time, zero_setup_time] = sh.setup_time()

        OPTS.check_lvsdrc = True
        if OPTS.tech_name == "freepdk45":
            self.assertTrue(isclose(one_setup_time, 0.0146484375))
            self.assertTrue(isclose(zero_setup_time, 0.008544921875))
        elif OPTS.tech_name == "scn3me_subm":
            self.assertTrue(isclose(one_setup_time, 0.0927734375))
            self.assertTrue(isclose(zero_setup_time, -0.0244140625))
        else:
            self.assertTrue(False)  # other techs fail

        globals.end_openram()
Example #3
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "hspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram

        debug.info(1,
                   "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="test_sram1")

        OPTS.check_lvsdrc = True

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(
            1,
            "Probe address {0} probe data {1}".format(probe_address,
                                                      probe_data))

        d = delay.delay(s, tempspice)
        data = d.analyze(probe_address, probe_data)

        if OPTS.tech_name == "freepdk45":
            self.assertTrue(isclose(data['delay1'], 0.013649))
            self.assertTrue(isclose(data['delay0'], 0.22893))
            self.assertTrue(isclose(data['min_period1'], 0.078582763671875))
            self.assertTrue(isclose(data['min_period0'], 0.25543212890625))
        elif OPTS.tech_name == "scn3me_subm":
            self.assertTrue(isclose(data['delay1'], 1.5335))
            self.assertTrue(isclose(data['delay0'], 2.2635000000000005))
            self.assertTrue(isclose(data['min_period1'], 1.53564453125))
            self.assertTrue(isclose(data['min_period0'], 2.998046875))
        else:
            self.assertTrue(False)  # other techs fail

        os.remove(tempspice)

        globals.end_openram()
Example #4
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "ngspice"
        globals.set_spice()

        import sram
        import tech
        slews = [tech.spice["rise_time"] * 2]

        import setup_hold

        sh = setup_hold.setup_hold()
        data = sh.analyze(slews, slews)

        if OPTS.tech_name == "freepdk45":
            golden_data = {
                'setup_times_LH': [0.01464844],
                'hold_times_LH': [0.0024414059999999997],
                'hold_times_HL': [-0.003662109],
                'setup_times_HL': [0.008544922]
            }
        elif OPTS.tech_name == "scn3me_subm":
            golden_data = {
                'setup_times_LH': [0.1000977],
                'hold_times_LH': [0.02075195],
                'hold_times_HL': [-0.08300781],
                'setup_times_HL': [0.02075195]
            }
        else:
            self.assertTrue(False)  # other techs fail

        # Check if no too many or too few results
        self.assertTrue(len(data.keys()) == len(golden_data.keys()))
        # Check each result
        for k in data.keys():
            if type(data[k]) == list:
                for i in range(len(data[k])):
                    self.assertTrue(isclose(data[k][i], golden_data[k][i]))
            else:
                self.assertTrue(isclose(data[k], golden_data[k]))

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        globals.set_spice()
        globals.end_openram()
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "ngspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram
        import tech
        slews = [tech.spice["rise_time"] * 2]

        import setup_hold

        sh = setup_hold.setup_hold()
        data = sh.analyze(slews, slews)

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        globals.set_spice()

        one_setup_time = data['setup_times_LH'][0]
        zero_setup_time = data['setup_times_HL'][0]
        one_hold_time = data['hold_times_LH'][0]
        zero_hold_time = data['hold_times_HL'][0]

        if OPTS.tech_name == "freepdk45":
            self.assertTrue(isclose(one_setup_time, 0.0146))
            self.assertTrue(isclose(zero_setup_time, 0.0085))
            self.assertTrue(isclose(one_hold_time, 0.00244))
            self.assertTrue(isclose(zero_hold_time, -0.00366))
        elif OPTS.tech_name == "scn3me_subm":
            self.assertTrue(isclose(one_setup_time, 0.1001))
            self.assertTrue(isclose(zero_setup_time, 0.0208))
            self.assertTrue(isclose(one_hold_time, 0.02075))
            self.assertTrue(isclose(zero_hold_time, -0.08301))
        else:
            self.assertTrue(False)  # other techs fail
Example #6
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "hspice"
        OPTS.force_spice = True
        OPTS.analytical_delay = False
        globals.set_spice()

        import sram

        debug.info(1,
                   "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="sram1")

        OPTS.check_lvsdrc = True

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(
            1,
            "Probe address {0} probe data {1}".format(probe_address,
                                                      probe_data))

        d = delay.delay(s, tempspice)
        import tech
        loads = [tech.spice["FF_in_cap"] * 4]
        slews = [tech.spice["rise_time"] * 2]
        data = d.analyze(probe_address, probe_data, slews, loads)

        if OPTS.tech_name == "freepdk45":
            golden_data = {
                'read1_power': 0.025833000000000002,
                'read0_power': 0.026039,
                'write0_power': 0.024105,
                'delay1': [0.047506],
                'delay0': [0.13799999999999998],
                'min_period': 0.322,
                'write1_power': 0.024214,
                'slew0': [0.026966],
                'slew1': [0.019338]
            }
        elif OPTS.tech_name == "scn3me_subm":
            golden_data = {
                'read1_power': 3.1765,
                'read0_power': 3.1929,
                'write0_power': 2.874,
                'delay1': [0.8900045999999999],
                'delay0': [1.9975000000000003],
                'min_period': 5.781,
                'write1_power': 2.6611,
                'slew0': [1.2993000000000001],
                'slew1': [0.9903856]
            }
        else:
            self.assertTrue(False)  # other techs fail
        # Check if no too many or too few results
        self.assertTrue(len(data.keys()) == len(golden_data.keys()))
        # Check each result
        for k in data.keys():
            if type(data[k]) == list:
                for i in range(len(data[k])):
                    self.assertTrue(isclose(data[k][i], golden_data[k][i]))
            else:
                self.assertTrue(isclose(data[k], golden_data[k]))

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        OPTS.analytical_delay = True
        globals.set_spice()

        os.remove(tempspice)

        globals.end_openram()
Example #7
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "ngspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram

        debug.info(1,
                   "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="test_sram1")

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(
            1,
            "Probe address {0} probe data {1}".format(probe_address,
                                                      probe_data))

        d = delay.delay(s, tempspice)
        import tech
        loads = [tech.spice["FF_in_cap"] * 4]
        slews = [tech.spice["rise_time"] * 2]
        data = d.analyze(probe_address, probe_data, slews, loads)

        if OPTS.tech_name == "freepdk45":
            self.assertTrue(isclose(data['delay1'][0],
                                    0.0268))  # diff than hspice
            self.assertTrue(isclose(data['delay0'][0],
                                    0.1127))  # diff than hspice
            self.assertTrue(isclose(data['slew1'][0],
                                    0.0231))  # diff than hspice
            self.assertTrue(isclose(data['slew0'][0],
                                    0.0276))  # diff than hspice
            self.assertTrue(isclose(data['min_period'],
                                    0.071))  # diff than hspice
            self.assertTrue(isclose(data['read0_power'],
                                    0.0227))  # diff than hspice
            self.assertTrue(isclose(data['read1_power'],
                                    0.0223))  # diff than hspice
            self.assertTrue(isclose(data['write0_power'],
                                    0.02001))  # diff than hspice
            self.assertTrue(isclose(data['write1_power'],
                                    0.0193))  # diff than hspice
        elif OPTS.tech_name == "scn3me_subm":
            self.assertTrue(isclose(data['delay1'][0],
                                    0.6228))  # diff than hspice
            self.assertTrue(isclose(data['delay0'][0],
                                    1.4147))  # diff than hspice
            self.assertTrue(isclose(data['slew1'][0],
                                    1.0567))  # diff than hspice
            self.assertTrue(isclose(data['slew0'][0],
                                    1.3454))  # diff than hspice
            self.assertTrue(isclose(data['min_period'],
                                    1.719))  # diff than hspice
            self.assertTrue(isclose(data['read0_power'],
                                    4.7812))  # diff than hspice
            self.assertTrue(isclose(data['read1_power'],
                                    5.5500))  # diff than hspice
            self.assertTrue(isclose(data['write0_power'],
                                    3.9314))  # diff than hspice
            self.assertTrue(isclose(data['write1_power'],
                                    3.4097))  # diff than hspice
        else:
            self.assertTrue(False)  # other techs fail

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        globals.set_spice()

        os.remove(tempspice)

        globals.end_openram()
Example #8
0
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version="ngspice"
        OPTS.force_spice = True
        OPTS.analytical_delay = False
        globals.set_spice()
        
        import sram

        debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="sram1")

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))

        d = delay.delay(s,tempspice)
        import tech
        loads = [tech.spice["FF_in_cap"]*4]
        slews = [tech.spice["rise_time"]*2]
        data = d.analyze(probe_address, probe_data,slews,loads)

        if OPTS.tech_name == "freepdk45":
            golden_data = {'read1_power': 0.02527215,
                           'read0_power': 0.02573022,
                           'write0_power': 0.02237065,
                           'delay1': [0.04867785],
                           'delay0': [0.1423512],
                           'min_period': 0.332,
                           'write1_power': 0.02152122,
                           'slew0': [0.0273352],
                           'slew1': [0.021216870000000002]}
        elif OPTS.tech_name == "scn3me_subm":
            golden_data = {'read1_power': 3.244839,
                           'read0_power': 3.088234,
                           'write0_power': 2.6857420000000003,
                           'delay1': [0.9200643],
                           'delay0': [2.0509399999999998],
                           'min_period': 6.563,
                           'write1_power': 2.378355,
                           'slew0': [1.342019],
                           'slew1': [1.040885]}
        else:
            self.assertTrue(False) # other techs fail

        # Check if no too many or too few results
        self.assertTrue(len(data.keys())==len(golden_data.keys()))
        # Check each result
        for k in data.keys():
            if type(data[k])==list:
                for i in range(len(data[k])):
                    self.assertTrue(isclose(data[k][i],golden_data[k][i]))
            else:
                self.assertTrue(isclose(data[k],golden_data[k]))

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version="hspice"
        OPTS.force_spice = False
        OPTS.analytical_delay = True
        globals.set_spice()

        os.remove(tempspice)

        globals.end_openram()
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "hspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram

        debug.info(1,
                   "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="test_sram1")

        OPTS.check_lvsdrc = True

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(
            1,
            "Probe address {0} probe data {1}".format(probe_address,
                                                      probe_data))

        d = delay.delay(s, tempspice)
        import tech
        loads = [tech.spice["FF_in_cap"] * 4]
        slews = [tech.spice["rise_time"] * 2]
        data = d.analyze(probe_address, probe_data, slews, loads)

        if OPTS.tech_name == "freepdk45":
            golden_data = {
                'read1_power': 0.017787999999999998,
                'read0_power': 0.017827,
                'write0_power': 0.016626,
                'delay1': [0.02616],
                'delay0': [0.10966999999999999],
                'min_period': 0.264,
                'write1_power': 0.015919000000000003,
                'slew0': [0.027029],
                'slew1': [0.021002999999999997]
            }
        elif OPTS.tech_name == "scn3me_subm":
            golden_data = {
                'read1_power': 4.5206,
                'read0_power': 4.5492,
                'write0_power': 3.8564,
                'delay1': [0.5985562],
                'delay0': [1.3725000000000003],
                'min_period': 4.531,
                'write1_power': 3.7291,
                'slew0': [1.3013000000000001],
                'slew1': [1.0045]
            }
        else:
            self.assertTrue(False)  # other techs fail
        # Check if no too many or too few results
        self.assertTrue(len(data.keys()) == len(golden_data.keys()))
        # Check each result
        for k in data.keys():
            if type(data[k]) == list:
                for i in range(len(data[k])):
                    self.assertTrue(isclose(data[k][i], golden_data[k][i]))
            else:
                self.assertTrue(isclose(data[k], golden_data[k]))

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        globals.set_spice()

        os.remove(tempspice)

        globals.end_openram()
    def runTest(self):
        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
        # we will manually run lvs/drc
        OPTS.check_lvsdrc = False
        OPTS.spice_version = "ngspice"
        OPTS.force_spice = True
        globals.set_spice()

        import sram

        debug.info(1,
                   "Testing timing for sample 1bit, 16words SRAM with 1 bank")
        s = sram.sram(word_size=OPTS.config.word_size,
                      num_words=OPTS.config.num_words,
                      num_banks=OPTS.config.num_banks,
                      name="test_sram1")

        import delay

        tempspice = OPTS.openram_temp + "temp.sp"
        s.sp_write(tempspice)

        probe_address = "1" * s.addr_size
        probe_data = s.word_size - 1
        debug.info(
            1,
            "Probe address {0} probe data {1}".format(probe_address,
                                                      probe_data))

        d = delay.delay(s, tempspice)
        import tech
        loads = [tech.spice["FF_in_cap"] * 4]
        slews = [tech.spice["rise_time"] * 2]
        data = d.analyze(probe_address, probe_data, slews, loads)

        if OPTS.tech_name == "freepdk45":
            golden_data = {
                'read1_power': 0.022260799999999997,
                'read0_power': 0.02274298,
                'write0_power': 0.02000899,
                'delay1': [0.026754629999999998],
                'delay0': [0.1126814],
                'min_period': 0.273,
                'write1_power': 0.01934197,
                'slew0': [0.02760651],
                'slew1': [0.023076919999999997]
            }
        elif OPTS.tech_name == "scn3me_subm":
            golden_data = {
                'read1_power': 5.549996,
                'read0_power': 4.781156,
                'write0_power': 3.931431,
                'delay1': [0.6227914],
                'delay0': [1.414657],
                'min_period': 4.688,
                'write1_power': 3.409661,
                'slew0': [1.345377],
                'slew1': [1.05667]
            }
        else:
            self.assertTrue(False)  # other techs fail

        # Check if no too many or too few results
        self.assertTrue(len(data.keys()) == len(golden_data.keys()))
        # Check each result
        for k in data.keys():
            if type(data[k]) == list:
                for i in range(len(data[k])):
                    self.assertTrue(isclose(data[k][i], golden_data[k][i]))
            else:
                self.assertTrue(isclose(data[k], golden_data[k]))

        # reset these options
        OPTS.check_lvsdrc = True
        OPTS.spice_version = "hspice"
        OPTS.force_spice = False
        globals.set_spice()

        os.remove(tempspice)

        globals.end_openram()