def print_kernel_xml(top_name, ports, kernel_xml):
"""Generate kernel.xml file.
Args:
top_name: name of the top-level kernel function.
ports: sequence of (port_name, bundle_name, haoda_type, _) of m_axi ports
kernel_xml: file object to write to.
"""
m_axi_ports = ''
args = ''
offset = 0x10
arg_id = 0
bundle_set = set()
for port_name, bundle_name, haoda_type, _ in ports:
size = host_size = 8
if bundle_name not in bundle_set:
m_axi_ports += PORT_TEMPLATE.format(
name=bundle_name,
width=util.get_width_in_bits(haoda_type)).rstrip('\n')
bundle_set.add(bundle_name)
args += ARG_TEMPLATE.format(
name=port_name, addr_qualifier=1, arg_id=arg_id,
port_name='m_axi_' + bundle_name, c_type=util.get_c_type(haoda_type),
size=size, offset=offset, host_size=host_size).rstrip('\n')
offset += size + 4
arg_id += 1
args += ARG_TEMPLATE.format(
name='coalesced_data_num', addr_qualifier=0, arg_id=arg_id,
port_name='s_axi_control', c_type='uint64_t', size=size, offset=offset,
host_size=host_size).rstrip('\n')
kernel_xml.write(KERNEL_XML_TEMPLATE.format(
top_name=top_name, m_axi_ports=m_axi_ports, args=args))
def mutate_dram_ref_for_writes(obj, kwargs):
if isinstance(obj, ir.DRAMRef):
coalescing_idx = kwargs.pop('coalescing_idx')
unroll_factor = kwargs.pop('unroll_factor')
type_width = util.get_width_in_bits(obj.haoda_type)
elem_idx = coalescing_idx * unroll_factor + obj.offset
num_banks = num_bank_map[obj.var]
bank = obj.dram[elem_idx % num_banks]
lsb = (elem_idx // num_banks) * type_width
msb = lsb + type_width - 1
return ir.Var(name='{}({msb}, {lsb})'.format(
obj.dram_buf_name(bank), msb=msb, lsb=lsb),
idx=())
return obj
def mutate_dram_ref_for_reads(obj, kwargs):
if isinstance(obj, ir.DRAMRef):
coalescing_idx = kwargs.pop('coalescing_idx')
unroll_factor = kwargs.pop('unroll_factor')
type_width = util.get_width_in_bits(obj.haoda_type)
elem_idx = coalescing_idx * unroll_factor + obj.offset
num_banks = num_bank_map[obj.var]
bank = expr.dram[elem_idx % num_banks]
lsb = (elem_idx // num_banks) * type_width
msb = lsb + type_width - 1
return ir.Var(
name='Reinterpret<{c_type}>(static_cast<ap_uint<{width} > >('
'{dram_buf_name}({msb}, {lsb})))'.format(
c_type=obj.c_type,
dram_buf_name=obj.dram_buf_name(bank),
msb=msb,
lsb=lsb,
width=msb - lsb + 1),
idx=())
return obj
def _print_module_definition(printer, module_trait, module_trait_id, **kwargs):
println = printer.println
do_scope = printer.do_scope
un_scope = printer.un_scope
func_name = util.get_func_name(module_trait_id)
func_lower_name = util.get_module_name(module_trait_id)
ii = 1
def get_delays(obj, delays):
if isinstance(obj, ir.DelayedRef):
delays.append(obj)
return obj
delays = []
for let in module_trait.lets:
let.visit(get_delays, delays)
for expr in module_trait.exprs:
expr.visit(get_delays, delays)
_logger.debug('delays: %s', delays)
fifo_loads = tuple(
'/* input*/ hls::stream<Data<{} > >* {}'.format(_.c_type, _.ld_name)
for _ in module_trait.loads)
fifo_stores = tuple('/*output*/ hls::stream<Data<{} > >* {}{}'.format(
expr.c_type, ir.FIFORef.ST_PREFIX, idx)
for idx, expr in enumerate(module_trait.exprs))
# look for DRAM access
reads_in_lets = tuple(_.expr for _ in module_trait.lets)
writes_in_lets = tuple(_.name for _ in module_trait.lets
if not isinstance(_.name, str))
reads_in_exprs = module_trait.exprs
dram_reads = visitor.get_dram_refs(reads_in_lets + reads_in_exprs)
dram_writes = visitor.get_dram_refs(writes_in_lets)
dram_read_map = collections.OrderedDict()
dram_write_map = collections.OrderedDict()
all_dram_reads = ()
num_bank_map = {}
if dram_reads: # this is an unpacking module
assert not dram_writes, 'cannot read and write DRAM in the same module'
for dram_read in dram_reads:
dram_read_map.setdefault(dram_read.var,
collections.OrderedDict()).setdefault(
dram_read.dram, []).append(dram_read)
_logger.debug('dram read map: %s', dram_read_map)
burst_width = kwargs.pop('burst_width')
for var in dram_read_map:
for dram in dram_read_map[var]:
# number of elements per cycle
batch_size = len(dram_read_map[var][dram])
dram_read_map[var][dram] = collections.OrderedDict(
(_.offset, _) for _ in dram_read_map[var][dram])
dram_reads = dram_read_map[var][dram]
num_banks = len(next(iter(dram_reads.values())).dram)
if var in num_bank_map:
assert num_bank_map[
var] == num_banks, 'inconsistent num banks'
else:
num_bank_map[var] = num_banks
_logger.debug('dram reads: %s', dram_reads)
assert tuple(sorted(dram_reads.keys())) == tuple(range(batch_size)), \
'unexpected DRAM accesses pattern %s' % dram_reads
batch_width = sum(
util.get_width_in_bits(_.haoda_type)
for _ in dram_reads.values())
del dram_reads
if burst_width * num_banks >= batch_width:
assert burst_width * num_banks % batch_width == 0, \
'cannot process such a burst'
# a single burst consumed in multiple cycles
coalescing_factor = burst_width * num_banks // batch_width
ii = coalescing_factor
else:
assert batch_width * num_banks % burst_width == 0, \
'cannot process such a burst'
# multiple bursts consumed in a single cycle
# reassemble_factor = batch_width // (burst_width * num_banks)
raise util.InternalError('cannot process such a burst yet')
dram_reads = tuple(
next(iter(_.values())) for _ in dram_read_map[var].values())
all_dram_reads += dram_reads
fifo_loads += tuple(
'/* input*/ hls::stream<Data<ap_uint<{burst_width} > > >* '
'{bank_name}'.format(burst_width=burst_width,
bank_name=_.dram_fifo_name(bank))
for _ in dram_reads for bank in _.dram)
elif dram_writes: # this is a packing module
for dram_write in dram_writes:
dram_write_map.setdefault(dram_write.var,
collections.OrderedDict()).setdefault(
dram_write.dram,
[]).append(dram_write)
_logger.debug('dram write map: %s', dram_write_map)
burst_width = kwargs.pop('burst_width')
for var in dram_write_map:
for dram in dram_write_map[var]:
# number of elements per cycle
batch_size = len(dram_write_map[var][dram])
dram_write_map[var][dram] = collections.OrderedDict(
(_.offset, _) for _ in dram_write_map[var][dram])
dram_writes = dram_write_map[var][dram]
num_banks = len(next(iter(dram_writes.values())).dram)
if var in num_bank_map:
assert num_bank_map[
var] == num_banks, 'inconsistent num banks'
else:
num_bank_map[var] = num_banks
_logger.debug('dram writes: %s', dram_writes)
assert tuple(sorted(dram_writes.keys())) == tuple(range(batch_size)), \
'unexpected DRAM accesses pattern %s' % dram_writes
batch_width = sum(
util.get_width_in_bits(_.haoda_type)
for _ in dram_writes.values())
del dram_writes
if burst_width * num_banks >= batch_width:
assert burst_width * num_banks % batch_width == 0, \
'cannot process such a burst'
# a single burst consumed in multiple cycles
coalescing_factor = burst_width * num_banks // batch_width
ii = coalescing_factor
else:
assert batch_width * num_banks % burst_width == 0, \
'cannot process such a burst'
# multiple bursts consumed in a single cycle
# reassemble_factor = batch_width // (burst_width * num_banks)
raise util.InternalError('cannot process such a burst yet')
dram_writes = tuple(
next(iter(_.values())) for _ in dram_write_map[var].values())
fifo_stores += tuple(
'/*output*/ hls::stream<Data<ap_uint<{burst_width} > > >* '
'{bank_name}'.format(burst_width=burst_width,
bank_name=_.dram_fifo_name(bank))
for _ in dram_writes for bank in _.dram)
# print function
printer.print_func('void {func_name}'.format(**locals()),
fifo_stores + fifo_loads,
align=0)
do_scope(func_name)
for dram_ref, bank in module_trait.dram_writes:
println(
'#pragma HLS data_pack variable = {}'.format(
dram_ref.dram_fifo_name(bank)), 0)
for arg in module_trait.output_fifos:
println('#pragma HLS data_pack variable = %s' % arg, 0)
for arg in module_trait.input_fifos:
println('#pragma HLS data_pack variable = %s' % arg, 0)
for dram_ref, bank in module_trait.dram_reads:
println(
'#pragma HLS data_pack variable = {}'.format(
dram_ref.dram_fifo_name(bank)), 0)
# print inter-iteration declarations
for delay in delays:
println(delay.c_buf_decl)
println(delay.c_ptr_decl)
# print loop
println('{}_epoch:'.format(func_lower_name), indent=0)
println('for (bool enable = true; enable;)')
do_scope('for {}_epoch'.format(func_lower_name))
println('#pragma HLS pipeline II=%d' % ii, 0)
for delay in delays:
println(
'#pragma HLS dependence variable=%s inter false' % delay.buf_name,
0)
# print emptyness tests
println(
'if (%s)' %
(' && '.join('!{fifo}->empty()'.format(fifo=fifo)
for fifo in tuple(_.ld_name
for _ in module_trait.loads) + tuple(
_.dram_fifo_name(bank)
for _ in all_dram_reads
for bank in _.dram))))
do_scope('if not empty')
# print intra-iteration declarations
for fifo_in in module_trait.loads:
println('{fifo_in.c_type} {fifo_in.ref_name};'.format(**locals()))
for var in dram_read_map:
for dram in (next(iter(_.values()))
for _ in dram_read_map[var].values()):
for bank in dram.dram:
println('ap_uint<{}> {};'.format(burst_width,
dram.dram_buf_name(bank)))
for var in dram_write_map:
for dram in (next(iter(_.values()))
for _ in dram_write_map[var].values()):
for bank in dram.dram:
println('ap_uint<{}> {};'.format(burst_width,
dram.dram_buf_name(bank)))
# print enable conditions
if not dram_write_map:
for fifo_in in module_trait.loads:
println('const bool {fifo_in.ref_name}_enable = '
'ReadData(&{fifo_in.ref_name}, {fifo_in.ld_name});'.format(
**locals()))
for dram in all_dram_reads:
for bank in dram.dram:
println('const bool {dram_buf_name}_enable = '
'ReadData(&{dram_buf_name}, {dram_fifo_name});'.format(
dram_buf_name=dram.dram_buf_name(bank),
dram_fifo_name=dram.dram_fifo_name(bank)))
if not dram_write_map:
println('const bool enabled = %s;' % (' && '.join(
tuple('{_.ref_name}_enable'.format(_=_)
for _ in module_trait.loads) +
tuple('{}_enable'.format(_.dram_buf_name(bank))
for _ in all_dram_reads for bank in _.dram))))
println('enable = enabled;')
# print delays (if any)
for delay in delays:
println('const {} {};'.format(delay.c_type, delay.c_buf_load))
# print lets
def mutate_dram_ref_for_writes(obj, kwargs):
if isinstance(obj, ir.DRAMRef):
coalescing_idx = kwargs.pop('coalescing_idx')
unroll_factor = kwargs.pop('unroll_factor')
type_width = util.get_width_in_bits(obj.haoda_type)
elem_idx = coalescing_idx * unroll_factor + obj.offset
num_banks = num_bank_map[obj.var]
bank = obj.dram[elem_idx % num_banks]
lsb = (elem_idx // num_banks) * type_width
msb = lsb + type_width - 1
return ir.Var(name='{}({msb}, {lsb})'.format(
obj.dram_buf_name(bank), msb=msb, lsb=lsb),
idx=())
return obj
# mutate dram ref for writes
if dram_write_map:
for coalescing_idx in range(coalescing_factor):
for fifo_in in module_trait.loads:
if coalescing_idx == coalescing_factor - 1:
prefix = 'const bool {fifo_in.ref_name}_enable = '.format(
fifo_in=fifo_in)
else:
prefix = ''
println('{prefix}ReadData(&{fifo_in.ref_name},'
' {fifo_in.ld_name});'.format(fifo_in=fifo_in,
prefix=prefix))
if coalescing_idx == coalescing_factor - 1:
println('const bool enabled = %s;' % (' && '.join(
tuple('{_.ref_name}_enable'.format(_=_)
for _ in module_trait.loads) +
tuple('{}_enable'.format(_.dram_buf_name(bank))
for _ in dram_reads for bank in _.dram))))
println('enable = enabled;')
for idx, let in enumerate(module_trait.lets):
let = let.visit(
mutate_dram_ref_for_writes, {
'coalescing_idx':
coalescing_idx,
'unroll_factor':
len(dram_write_map[let.name.var][let.name.dram])
})
println('{} = Reinterpret<ap_uint<{width} > >({});'.format(
let.name,
let.expr.c_expr,
width=util.get_width_in_bits(let.expr.haoda_type)))
for var in dram_write_map:
for dram in (next(iter(_.values()))
for _ in dram_write_map[var].values()):
for bank in dram.dram:
println('WriteData({}, {}, enabled);'.format(
dram.dram_fifo_name(bank), dram.dram_buf_name(bank)))
else:
for let in module_trait.lets:
println(let.c_expr)
def mutate_dram_ref_for_reads(obj, kwargs):
if isinstance(obj, ir.DRAMRef):
coalescing_idx = kwargs.pop('coalescing_idx')
unroll_factor = kwargs.pop('unroll_factor')
type_width = util.get_width_in_bits(obj.haoda_type)
elem_idx = coalescing_idx * unroll_factor + obj.offset
num_banks = num_bank_map[obj.var]
bank = expr.dram[elem_idx % num_banks]
lsb = (elem_idx // num_banks) * type_width
msb = lsb + type_width - 1
return ir.Var(
name='Reinterpret<{c_type}>(static_cast<ap_uint<{width} > >('
'{dram_buf_name}({msb}, {lsb})))'.format(
c_type=obj.c_type,
dram_buf_name=obj.dram_buf_name(bank),
msb=msb,
lsb=lsb,
width=msb - lsb + 1),
idx=())
return obj
# mutate dram ref for reads
if dram_read_map:
for coalescing_idx in range(coalescing_factor):
for idx, expr in enumerate(module_trait.exprs):
println('WriteData({}{}, {}, {});'.format(
ir.FIFORef.ST_PREFIX, idx,
expr.visit(
mutate_dram_ref_for_reads, {
'coalescing_idx':
coalescing_idx,
'unroll_factor':
len(dram_read_map[expr.var][expr.dram])
}).c_expr, 'true'
if coalescing_idx < coalescing_factor - 1 else 'enabled'))
else:
for idx, expr in enumerate(module_trait.exprs):
println('WriteData({}{}, {}({}), enabled);'.format(
ir.FIFORef.ST_PREFIX, idx, expr.c_type, expr.c_expr))
for delay in delays:
println(delay.c_buf_store)
println('{} = {};'.format(delay.ptr, delay.c_next_ptr_expr))
un_scope()
un_scope()
un_scope()
_logger.debug('printing: %s', module_trait)
def _print_interface(printer, kernel_name, inputs, outputs, super_source):
"""Prints the top-level module for the given arguments.
Prints the top-level interfaces and sub-module instances with proper interface
pragmas, hls::stream declarations and references, and module function calls.
Currently only streaming applications are supported.
Args:
printer: Printer to which the code is emitted.
kernel_name: str, name of the kernel.
inputs: Sequence of (name, c_type, bank, depth) tuples, specifies the m_axi
input interfaces.
outputs: Sequence of (name, c_type, bank, depth) tuples, specifies the m_axi
output interfaces.
super_source: SuperSourceNode of a DAG of HAODA nodes.
"""
println = printer.println
do_indent = printer.do_indent
un_indent = printer.un_indent
do_scope = printer.do_scope
un_scope = printer.un_scope
get_bundle_name = util.get_bundle_name
get_port_name = util.get_port_name
get_port_buf_name = util.get_port_buf_name
println('extern "C"')
println('{')
println()
println('void %s(' % kernel_name)
do_indent()
for name, c_type, bank, _ in outputs + inputs:
println('{}* {},'.format(c_type, get_port_name(name, bank)))
println('uint64_t coalesced_data_num)')
un_indent()
do_scope()
for name, c_type, bank, depth in outputs + inputs:
println(
'#pragma HLS interface m_axi port={} offset=slave depth={} bundle={'
'}'.format(get_port_name(name, bank), depth,
get_bundle_name(name, bank)), 0)
println()
for name, _, bank, _ in outputs + inputs:
println(
'#pragma HLS interface s_axilite port={} bundle=control'.format(
get_port_name(name, bank)), 0)
println(
'#pragma HLS interface s_axilite port=coalesced_data_num '
'bundle=control', 0)
println('#pragma HLS interface s_axilite port=return bundle=control', 0)
println()
# port buf declarations
for name, c_type, bank, _ in inputs + outputs:
println('hls::stream<Data<{c_type} > > {name}("{name}");'.format(
name=get_port_buf_name(name, bank), c_type=c_type))
# port buf depths
println(
'#pragma HLS stream variable={} depth=32'.format(
get_port_buf_name(name, bank)), 0)
println('#pragma HLS data_pack variable={}'.format(
get_port_buf_name(name, bank)),
indent=0)
println()
# internal fifos
for node in super_source.tpo_node_gen():
for fifo in node.fifos:
println('hls::stream<Data<{0} > > {1}("{1}");'.format(
fifo.c_type, fifo.c_expr))
println(
'#pragma HLS stream variable={} depth={}'.format(
fifo.c_expr,
max(fifo.depth,
512 // util.get_width_in_bits(fifo.haoda_type))), 0)
println('#pragma HLS data_pack variable={}'.format(fifo.c_expr),
indent=0)
println()
println('#pragma HLS dataflow', 0)
for name, _, bank, _ in inputs:
println('BurstRead(&{}, {}, coalesced_data_num);'.format(
get_port_buf_name(name, bank), get_port_name(name, bank)))
for node in super_source.tpo_node_gen():
module_trait_id = super_source.module_table[node][1]
_print_module_func_call(printer, node, module_trait_id)
for name, _, bank, _ in outputs:
println('BurstWrite({}, &{}, coalesced_data_num);'.format(
get_port_name(name, bank), get_port_buf_name(name, bank)))
un_scope()
println()
println('}//extern "C"')
def print_top_module(printer, super_source, inputs, outputs):
println = printer.println
println('`timescale 1 ns / 1 ps')
args = [
'ap_clk', 'ap_rst', 'ap_start', 'ap_done', 'ap_continue', 'ap_idle',
'ap_ready'
]
for port_name, _, _, _ in outputs:
args.append('{}_V_V{data_in}'.format(port_name, **FIFO_PORT_SUFFIXES))
args.append('{}_V_V{not_full}'.format(port_name, **FIFO_PORT_SUFFIXES))
args.append('{}_V_V{write_enable}'.format(port_name,
**FIFO_PORT_SUFFIXES))
for port_name, _, _, _ in inputs:
args.append('{}_V_V{data_out}'.format(port_name, **FIFO_PORT_SUFFIXES))
args.append('{}_V_V{not_empty}'.format(port_name,
**FIFO_PORT_SUFFIXES))
args.append('{}_V_V{read_enable}'.format(port_name,
**FIFO_PORT_SUFFIXES))
printer.module('Dataflow', args)
println()
input_args = 'ap_clk', 'ap_rst', 'ap_start', 'ap_continue'
output_args = 'ap_done', 'ap_idle', 'ap_ready'
for arg in input_args:
println('input %s;' % arg)
for arg in output_args:
println('output %s;' % arg)
for port_name, _, haoda_type, _ in outputs:
kwargs = dict(port_name=port_name, **FIFO_PORT_SUFFIXES)
println('output [{}:0] {port_name}_V_V{data_in};'.format(
util.get_width_in_bits(haoda_type) - 1, **kwargs))
println('input {port_name}_V_V{not_full};'.format(**kwargs))
println('output {port_name}_V_V{write_enable};'.format(**kwargs))
for port_name, _, haoda_type, _ in inputs:
kwargs = dict(port_name=port_name, **FIFO_PORT_SUFFIXES)
println('input [{}:0] {port_name}_V_V{data_out};'.format(
util.get_width_in_bits(haoda_type) - 1, **kwargs))
println('input {port_name}_V_V{not_empty};'.format(**kwargs))
println('output {port_name}_V_V{read_enable};'.format(**kwargs))
println()
println("reg ap_done = 1'b0;")
println("reg ap_idle = 1'b1;")
println("reg ap_ready = 1'b0;")
for port_name, _, haoda_type, _ in outputs:
kwargs = dict(port_name=port_name, **FIFO_PORT_SUFFIXES)
println('reg [{}:0] {port_name}{data_in};'.format(
util.get_width_in_bits(haoda_type) - 1, **kwargs))
println('wire {port_name}_V_V{write_enable};'.format(**kwargs))
for port_name, _, haoda_type, _ in inputs:
println('wire {}_V_V{read_enable};'.format(port_name,
**FIFO_PORT_SUFFIXES))
println('reg ap_rst_n_inv;')
with printer.always('*'):
println('ap_rst_n_inv = ap_rst;')
println()
with printer.always('posedge ap_clk'):
with printer.if_('ap_rst'):
println("ap_done <= 1'b0;")
println("ap_idle <= 1'b1;")
println("ap_ready <= 1'b0;")
printer.else_()
println('ap_idle <= ~ap_start;')
for port_name, _, _, _ in outputs:
println('reg {}_V_V{not_block};'.format(port_name,
**FIFO_PORT_SUFFIXES))
for port_name, _, _, _ in inputs:
println('reg {}_V_V{not_block};'.format(port_name,
**FIFO_PORT_SUFFIXES))
with printer.always('*'):
for port_name, _, _, _ in outputs:
println('{port_name}_V_V{not_block} = {port_name}_V_V{not_full};'.
format(port_name=port_name, **FIFO_PORT_SUFFIXES))
for port_name, _, _, _ in inputs:
println('{port_name}_V_V{not_block} = {port_name}_V_V{not_empty};'.
format(port_name=port_name, **FIFO_PORT_SUFFIXES))
println()
for module in super_source.tpo_node_gen():
for fifo in module.fifos:
kwargs = {
'name': fifo.c_expr,
'msb': fifo.width_in_bits - 1,
**FIFO_PORT_SUFFIXES
}
println('wire [{msb}:0] {name}{data_in};'.format(**kwargs))
println('wire {name}{not_full};'.format(**kwargs))
println('wire {name}{write_enable};'.format(**kwargs))
println('wire [{msb}:0] {name}{data_out};'.format(**kwargs))
println('wire {name}{not_empty};'.format(**kwargs))
println('wire {name}{read_enable};'.format(**kwargs))
println()
args = collections.OrderedDict(
(('clk', 'ap_clk'), ('reset', 'ap_rst_n_inv'), ('if_read_ce',
"1'b1"),
('if_write_ce', "1'b1"), ('if{data_in}'.format(**kwargs),
'{name}{data_in}'.format(**kwargs)),
('if{not_full}'.format(**kwargs),
'{name}{not_full}'.format(**kwargs)),
('if{write_enable}'.format(**kwargs),
'{name}{write_enable}'.format(**kwargs)),
('if{data_out}'.format(**kwargs),
'{name}{data_out}'.format(**kwargs)),
('if{not_empty}'.format(**kwargs),
'{name}{not_empty}'.format(**kwargs)),
('if{read_enable}'.format(**kwargs),
'{name}{read_enable}'.format(**kwargs))))
printer.module_instance(
'fifo_w{width}_d{depth}_A'.format(width=fifo.width_in_bits,
depth=fifo.depth + 2),
fifo.c_expr, args)
println()
for module in super_source.tpo_node_gen():
module_trait, module_trait_id = super_source.module_table[module]
args = collections.OrderedDict(
(('ap_clk', 'ap_clk'), ('ap_rst', 'ap_rst_n_inv'), ('ap_start',
"1'b1")))
for dram_ref, bank in module.dram_writes:
kwargs = dict(port=dram_ref.dram_fifo_name(bank),
fifo=util.get_port_name(dram_ref.var, bank),
**FIFO_PORT_SUFFIXES)
args['{port}_V{data_in}'.format(**kwargs)] = \
'{fifo}_V_V{data_in}'.format(**kwargs)
args['{port}_V{not_full}'.format(**kwargs)] = \
'{fifo}_V_V{not_full}'.format(**kwargs)
args['{port}_V{write_enable}'.format(**kwargs)] = \
'{fifo}_V_V{write_enable}'.format(**kwargs)
for port, fifo in zip(module_trait.output_fifos, module.output_fifos):
kwargs = dict(port=port, fifo=fifo, **FIFO_PORT_SUFFIXES)
args['{port}_V{data_in}'.format(**kwargs)] = \
'{fifo}{data_in}'.format(**kwargs)
args['{port}_V{not_full}'.format(**kwargs)] = \
'{fifo}{not_full}'.format(**kwargs)
args['{port}_V{write_enable}'.format(**kwargs)] = \
'{fifo}{write_enable}'.format(**kwargs)
for port, fifo in zip(module_trait.input_fifos, module.input_fifos):
kwargs = dict(port=port, fifo=fifo, **FIFO_PORT_SUFFIXES)
args['{port}_V{data_out}'.format(**kwargs)] = \
"{{1'b1, {fifo}{data_out}}}".format(**kwargs)
args['{port}_V{not_empty}'.format(**kwargs)] = \
'{fifo}{not_empty}'.format(**kwargs)
args['{port}_V{read_enable}'.format(**kwargs)] = \
'{fifo}{read_enable}'.format(**kwargs)
for dram_ref, bank in module.dram_reads:
kwargs = dict(port=dram_ref.dram_fifo_name(bank),
fifo=util.get_port_name(dram_ref.var, bank),
**FIFO_PORT_SUFFIXES)
args['{port}_V{data_out}'.format(**kwargs)] = \
"{{1'b1, {fifo}_V_V{data_out}}}".format(**kwargs)
args['{port}_V{not_empty}'.format(**kwargs)] = \
'{fifo}_V_V{not_empty}'.format(**kwargs)
args['{port}_V{read_enable}'.format(**kwargs)] = \
'{fifo}_V_V{read_enable}'.format(**kwargs)
printer.module_instance(util.get_func_name(module_trait_id),
module.name, args)
println()
printer.endmodule()
fifos = set()
for module in super_source.tpo_node_gen():
for fifo in module.fifos:
fifos.add((fifo.width_in_bits, fifo.depth + 2))
for fifo in fifos:
printer.fifo_module(*fifo)
def width_in_bits(self):
return util.get_width_in_bits(self.haoda_type)
