def visit_type(self, t):
"""
:type t: iHdlExpr
"""
t, array_dims = collect_array_dims(t)
wire_params = get_wire_t_params(t)
if wire_params is None:
if t == HdlTypeAuto:
t = HdlTypeBitsDef(1)
else:
base_t, msb, is_signed, _ = wire_params
lsb = 0
if msb is None:
msb = 0
elif isinstance(msb, HdlOp):
if msb.fn == HdlOpType.DOWNTO:
msb, lsb = msb.ops
elif msb.fn == HdlOpType.TO:
lsb, msb = msb.ops
elif msb.fn == HdlOpType.CALL and msb.ops[0] == HdlValueId(
"slice"):
lsb = msb.ops[2]
msb = hdl_sub_int(msb.ops[1], 1)
t = HdlTypeBitsDef(msb, lsb=lsb, signed=is_signed)
for i in array_dims:
t = hdl_index(t, i)
return t
def visit_type_first_part(self, t):
"""
:type t: iHdlExpr
:return: True if the type has also the array dimension part
"""
w = self.out.write
t, array_dims = collect_array_dims(t)
wire_params = get_wire_t_params(t)
if wire_params is None:
if t != HdlTypeAuto:
if isinstance(t, HdlOp) and t.fn == HdlOpType.TYPE_OF:
w("var ")
self.visit_iHdlExpr(t)
else:
base_t, width, is_signed, _ = wire_params
if base_t is not HdlTypeAuto:
w(base_t.val)
if is_signed is None:
pass
elif is_signed:
w(" signed")
else:
w(" unsigned")
if width is not None:
# 1D vector
w("[")
self.visit_iHdlExpr(width)
w("]")
return len(array_dims) > 0
def visit_type_array_part(self, t):
"""
:type t: iHdlExpr
"""
w = self.out.write
_, array_dim = collect_array_dims(t)
for ad in array_dim:
w("[")
if ad is not None:
self.visit_iHdlExpr(ad)
w("]")
def visit_type(self, t):
"""
:type t: iHdlExpr
"""
t, array_dims = collect_array_dims(t)
wire_params = get_wire_t_params(t)
if wire_params is None:
if t == HdlTypeAuto:
t = BitsT(1)
else:
base_t, width, is_signed, _ = wire_params
if width is None:
width = 1
t = BitsT(width, is_signed)
for i in array_dims:
t = apply_index(t, i)
return t
def visit_HdlIdDef(self, var):
"""
:type var: HdlIdDef
"""
self.visit_doc(var)
w = self.out.write
t, arr_dims = collect_array_dims(var.type)
self.visit_type(t)
w(" ")
w(var.name)
for d in arr_dims:
w("[")
self.visit_iHdlExpr(d)
w("]")
if var.value is not None:
w(" = ")
with Indent(self.out):
self.visit_iHdlExpr(var.value)
return True
def visit_type_declr(self, var):
"""
:type var: HdlIdDef
"""
assert var.type == HdlTypeType
self.visit_doc(var)
w = self.out.write
w("typedef ")
t, arr_dims = collect_array_dims(var.value)
with Indent(self.out):
self.visit_iHdlExpr(t)
w(" ")
w(var.name)
for d in arr_dims:
w("[")
self.visit_iHdlExpr(d)
w("]")
return True
def pop_index_list(self, o):
"""
:type o: iHdlExpr
"""
return collect_array_dims(o)
