def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
with ValueWidthRequirementScope(self, o == AllOps.CONCAT):
if o in self._cast_ops:
op0 = hdl_getattr(self.as_hdl(ops[0]), "_reinterpret_cast")
op1 = self.as_hdl_HdlType(op.result._dtype)
return hdl_call(op0, [op1, ])
elif o == AllOps.EQ:
return hdl_call(hdl_getattr(self.as_hdl(ops[0]), "_eq"),
[self.as_hdl(ops[1])])
elif o == AllOps.CONCAT:
return hdl_call(self.CONCAT,
[self.as_hdl(o2) for o2 in ops])
elif o == AllOps.TERNARY:
cond, op0, op1 = ops
cond = self.as_hdl(cond)
with ValueWidthRequirementScope(self, True):
op0 = self.as_hdl(op0)
op1 = self.as_hdl(op1)
return hdl_call(hdl_getattr(cond, "_ternary"), [op0, op1])
else:
o = self.op_transl_dict[o]
return HdlOp(o, [self.as_hdl(o2)
for o2 in ops])
def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
if o == AllOps.INDEX:
assert len(ops) == 2
o0, o1 = ops
if o1._dtype == SLICE:
# index to .range(x, y)
o0_hdl = self.as_hdl_operand(o0, 0, op)
o0_hdl = hdl_getattr(o0_hdl, "range")
return hdl_call(o0_hdl, [self.as_hdl_Value(o1.val.start),
self.as_hdl_Value(o1.val.stop)])
else:
return ToHdlAstVerilog_ops.as_hdl_Operator(self, op)
elif o in ToHdlAstHwt_ops._cast_ops:
assert len(ops) == 1, ops
t = self.as_hdl_HdlType(op.result._dtype)
return hdl_call(
HdlOp(HdlOpType.PARAMETRIZATION, [self.static_cast, t]),
[self.as_hdl_Value(ops[0]), ])
elif o == AllOps.CONCAT:
isNew, o = self.tmpVars.create_var_cached("tmpConcat_",
op.result._dtype,
postponed_init=True,
extra_args=(AllOps.CONCAT, op.result))
if isNew:
o.drivers.append(Assignment(op, o, virtual_only=True))
self.tmpVars.finish_var_init(o)
return self.as_hdl(o)
else:
return ToHdlAstVerilog_ops.as_hdl_Operator(self, op)
def as_hdl_BitsVal(self, val: BitsVal):
dtype = val._dtype
as_hdl_int = self.as_hdl_int
t = hdl_call(self.Bits3t, [
as_hdl_int(dtype.bit_length()), as_hdl_int(int(bool(dtype.signed)))])
return hdl_call(self.Bits3val, [t,
as_hdl_int(val.val),
as_hdl_int(val.vld_mask)])
def as_hdl_SignalItem(self, si, declaration=False):
assert(declaration == False)
if si.hidden:
assert si.origin is not None, si
return self.as_hdl(si.origin)
else:
id_ = hdl_call(self._id, [f'MODELPARAM_VALUE.{si.name}'])
return hdl_call(self._spirit_decode, [id_])
def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
if o == AllOps.TERNARY:
zero, one = BIT.from_py(0), BIT.from_py(1)
if ops[1] == one and ops[2] == zero:
# ignore redundant x ? 1 : 0
return self.as_hdl_cond(ops[0], True)
else:
op0 = self.as_hdl_cond(ops[0], True)
op1 = self.as_hdl_operand(ops[1], 1, op)
op2 = self.as_hdl_operand(ops[2], 2, op)
return HdlOp(HdlOpType.TERNARY, [op0, op1, op2])
elif o == AllOps.RISING_EDGE or o == AllOps.FALLING_EDGE:
raise UnsupportedEventOpErr()
elif o in [AllOps.BitsAsUnsigned, AllOps.BitsAsVec, AllOps.BitsAsSigned]:
op0, = ops
do_cast = bool(op0._dtype.signed) != bool(op.result._dtype.signed)
op_hdl = self.as_hdl_operand(op0, 0, op)
if do_cast:
if bool(op0._dtype.signed):
cast = self.SIGNED
else:
cast = self.UNSIGNED
return hdl_call(cast, [op_hdl, ])
else:
return op_hdl
else:
_o = self.op_transl_dict[o]
return HdlOp(_o, [self.as_hdl_operand(o2, i, op)
for i, o2 in enumerate(ops)])
def as_hdl_HdlType_bits(self, typ: Bits, declaration=False):
if declaration:
raise NotImplementedError()
if typ == BOOL:
return self.BOOL
if typ == INT:
return self.INT
w = typ.bit_length()
assert isinstance(w, int), w
def add_kw(name, val):
kw = hdl_map_asoc(HdlValueId(name),
HdlValueInt(val, None, None))
args.append(kw)
args = [HdlValueInt(w, None, None)]
if typ.signed is not BITS_DEFAUTL_SIGNED:
add_kw("signed", typ.signed)
if typ.force_vector is not BITS_DEFAUTL_FORCEVECTOR and w <= 1:
add_kw("force_vector", typ.force_vector)
if typ.negated is not BITS_DEFAUTL_NEGATED:
add_kw("negated", typ.negated)
return hdl_call(self.BITS, args)
def as_hdl_SliceVal(self, val):
args = (
val.val.start,
val.val.stop,
val.val.step
)
return hdl_call(self.SLICE, [self.as_hdl_int(int(a)) for a in args])
def as_hdl_HEnumVal(self, val: HEnumVal):
t_name = self.name_scope.get_object_name(val._dtype)
if val.vld_mask:
name = self.name_scope.get_object_name(val)
return hdl_getattr(hdl_getattr(self.SELF, t_name), name)
else:
return hdl_call(hdl_getattr(hdl_getattr(self.SELF, t_name), "from_py"),
[None, ])
def as_hdl_BitsVal(self, val):
t = val._dtype
w = t.bit_length()
_v = bit_string(val.val, w, val.vld_mask)
t = self.as_hdl_HdlType_bits(Bits(w, signed=t.signed))
return hdl_call(t, [
_v,
])
def as_hdl_BitString(self, v, width, force_vector, vld_mask, signed):
v = bit_string(v, width, vld_mask=vld_mask)
if signed:
return hdl_call(self.SIGNED, [
v,
])
else:
return v
def as_hdl_IfContainer_cond_eval(self, cond):
"""
constructs condition evaluation statement
c, cVld = sim_eval_cond(cond)
"""
c, cVld = self.C, self.CVLD
cond = self.as_hdl_cond(cond, True)
cond_eval = hdl_call(self.SIM_EVAL_COND, [cond])
cond_eval = HdlStmAssign(cond_eval, (c, cVld))
cond_eval.is_blocking = True
return c, cVld, cond_eval
def as_hdl_HdlType_bits(self, typ: Bits, declaration=False):
assert not declaration
w = typ.bit_length()
if isinstance(w, int):
pass
else:
w = int(w)
return hdl_call(self.BITS3T, [
HdlValueInt(w, None, None),
HdlValueInt(int(bool(typ.signed)), None, None)
])
def as_hdl_Operator(self, op: Operator):
ops = op.operands
o = op.operator
if o == AllOps.EQ:
op0 = self.as_hdl_Value(ops[0])
op1 = self.as_hdl_Value(ops[1])
return hdl_call(hdl_getattr(op0, "_eq"), [
op1,
])
elif o == AllOps.TERNARY:
zero, one = BIT.from_py(0), BIT.from_py(1)
if ops[1] == one and ops[2] == zero:
# ignore redundant x ? 1 : 0
return self.as_hdl_cond(ops[0], True)
else:
op0 = self.as_hdl_cond(ops[0], True)
op1 = self.as_hdl_Value(ops[1])
op2 = self.as_hdl_Value(ops[2])
return hdl_call(hdl_getattr(op0, "_ternary"), [op1, op2])
elif o == AllOps.RISING_EDGE or o == AllOps.FALLING_EDGE:
if o == AllOps.RISING_EDGE:
fn = "_onRisingEdge"
else:
fn = "_onFallingEdge"
op0 = self.as_hdl_Value(ops[0])
# pop .val
op0 = op0.ops[0]
return hdl_call(hdl_getattr(op0, fn), [])
elif o in [
AllOps.BitsAsUnsigned, AllOps.BitsAsVec, AllOps.BitsAsSigned
]:
op0, = ops
do_cast = bool(op0._dtype.signed) != bool(op.result._dtype.signed)
op_hdl = self.as_hdl_Value(op0)
if do_cast:
if bool(op0._dtype.signed):
sign = self.TRUE
else:
sign = self.FALSE
# cast_sign()
return hdl_call(hdl_getattr(op_hdl, "cast_sign"), [
sign,
])
else:
return op_hdl
elif o == AllOps.CONCAT:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_concat"),
[
self.as_hdl_Value(ops[1]),
])
elif o == AllOps.EQ:
return hdl_call(hdl_getattr(self.as_hdl_Value(ops[0]), "_eq"), [
self.as_hdl_Value(ops[1]),
])
else:
o = self.op_transl_dict[o]
return HdlOp(o, [self.as_hdl_Value(o2) for o2 in ops])
def as_hdl_SignalItem(self, si: SignalItem, declaration=False):
if declaration:
sigType = systemCTypeOfSig(si)
with SignalTypeSwap(self, sigType):
return ToHdlAst_Value.as_hdl_SignalItem(self, si, declaration=True)
else:
if si.hidden and si.origin is not None:
return self.as_hdl(si.origin)
else:
sigType = systemCTypeOfSig(si)
_si = HdlValueId(si.name, obj=si)
if self._in_sensitivity_list or self._is_target or sigType is SIGNAL_TYPE.REG:
return _si
else:
return hdl_call(hdl_getattr(_si, "read"), [])
def as_hdl_BitsVal(self, val: BitsVal):
isFullVld = val._is_full_valid()
if not self._valueWidthRequired:
if isFullVld:
return HdlValueInt(val.val, None, 16)
elif val.vld_mask == 0:
return self.NONE
t = self.as_hdl_HdlType_bits(val._dtype, declaration=False)
c = hdl_getattr(t, "from_py")
args = [HdlValueInt(val.val, None, 16), ]
if not isFullVld:
args.append(HdlValueInt(val.vld_mask, None, 16))
return hdl_call(c, args)
def _as_hdl_Assignment(self, dst, typeOfDst, src):
orig_is_target = self._is_target
try:
self._is_target = True
dst_hdl = self.as_hdl(dst)
finally:
self._is_target = orig_is_target
src_hdl = self.as_hdl_Value(src)
if typeOfDst == SIGNAL_TYPE.REG:
return HdlStmAssign(src_hdl, dst_hdl)
else:
return hdl_call(hdl_getattr(dst_hdl, "write"), [
src_hdl,
])
def as_hdl_HEnumVal(self, val: HEnumVal):
try:
t_name = self.name_scope.get_object_name(val._dtype)
except ObjectForNameNotFound:
if self.debug:
t_name = val._dtype.name
else:
raise
if val.vld_mask:
try:
name = self.name_scope.get_object_name(val)
except ObjectForNameNotFound:
if self.debug:
name = val.val
else:
raise
return hdl_getattr(HdlValueId(t_name, obj=val._dtype), name)
else:
return hdl_call(hdl_getattr(HdlValueId(t_name, obj=val._dtype), "from_py"),
[None, ])
def apply_cast(self, t_name, op):
return hdl_call(HdlValueId(t_name, obj=LanguageKeyword()),
[op, ])
def as_hdl_HArrayVal(self, val):
return hdl_call(self.Array3val, [
self.as_hdl_HdlType(val._dtype),
self.as_hdl_DictVal(val.val),
self.as_hdl_int(val.vld_mask)
])
def as_hdl_HdlType_float(self, typ: HFloat, declaration=False):
return hdl_call(HdlValueId("HFloat"), typ.exponent_w, typ.mantisa_w)