def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
MR = Signal(0, delay=10)
MW = Signal(0, delay=10)
address = Signal(intbv(0, 0, 2**32), delay=10)
WD = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
WD_driver = random_signal(clock, WD, seed=2)
MR_driver = pulse_generator(clock, MR, delay=2)
MW_driver = pulse_generator(clock, MW, delay=3)
py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD))
v_cosim = v_dm(clock, MR, MW, address, WD, vData)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def run_ALU_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
reset = Signal(0)
inA = Signal(intbv(0, 0, 2**32), delay=10)
inB = Signal(intbv(0, 0, 2**32), delay=10)
ALU_control = Signal(intbv(0, 0, 2**3), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
pyZero = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
vZero = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
control_driver = random_signal(clock, ALU_control, seed=1)
A_rand = random_signal(clock, inA, seed=2)
B_rand = random_signal(clock, inB, seed=3)
reset_driver = pulse_generator(clock, reset)
py_cosim = traceSignals(
py_alu(clock, reset, inA, inB, ALU_control, pyData, pyZero))
v_cosim = v_alu(clock, reset, ALU_control, inA, inB, vData, vZero)
read_test = match_test_report(clock, (vData, vZero), (pyData, pyZero),
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def run_hello_cosim():
clock = Signal(0)
clock_driver = clock_generator(clock)
din = Signal(intbv(val = 0, min = 0, max = 256))
rand = random_signal(clock, din)
doutver = Signal(intbv(val = 0, min = 0, max = 256))
v_cosim = accumulator_cosim(clock, din, doutver)
doutpy = Signal(modbv(val = 0, min = 0, max = 256))
py_cosim = Accumulator(clock, din, doutpy)
match_t = match_test(clock, doutver, doutpy)
sim = Simulation(clock_driver, rand, v_cosim, py_cosim, match_t)
sim.run(1000)
def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
infile = INDEX_256
clock = Signal(0)
address = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
py_cosim = traceSignals(py_im(clock, address, pyData, infile))
v_cosim = v_im(clock, address, vData, infile)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
from myhdl import Signal, Simulation, intbv, traceSignals
from MUX import MUX
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
if (__name__ == "__main__"):
MAX_CYCLES = 1000
#create signal variables
clk = Signal(0)
ctrl = Signal(0)
inputA = Signal(intbv(0, 0, 2**32))
inputB = Signal(intbv(0, 0, 2**32))
output = Signal(intbv(0, 0, 2**32))
#create drivers for variables
clock_driver = clock_generator(clk)
ctrl_driver = pulse_generator(clk, ctrl)
inputA_driver = random_signal(clk, inputA)
inputB_driver = random_signal(clk, inputB)
MUX_driver = traceSignals(MUX(ctrl, inputA, inputB, output))
#create and run simulation
sim = Simulation(clock_driver, ctrl_driver, inputA_driver, inputB_driver, MUX_driver)
sim.run(MAX_CYCLES)
ALU_out = Signal(intbv(0, 0, 2**32))
MemData_out = Signal(intbv(0, 0, 2**32))
reg_out = Signal(intbv(0, 0, 2**5))
zero_out = Signal(intbv(0, 0, 2**1))
PC_out = Signal(intbv(0, 0, 2**32))
MemToReg_out = Signal(intbv(0, 0, 2**1))
MemWrite_out = Signal(intbv(0, 0, 2**1))
WB_out = Signal(intbv(0, 0, 2**1))
clock_driver = clock_generator(clk)
register_driver = traceSignals(ex_mem(clk, ALU_in, ALU_out, MemData_in, MemData_out, reg_in,
reg_out, zero_in, zero_out, PC_in, PC_out, MemToReg_in,
MemToReg_out, MemWrite_in, MemWrite_out, WB_in, WB_out))
ALU_driver = random_signal(ALU_in, clk)
MemData_driver = random_signal(MemData_in, clk)
reg_driver = random_signal(reg_in, clk)
zero_driver = random_signal(zero_in, clk)
PC_driver = random_signal(PC_in, clk)
MemToReg_driver = random_signal(MemToReg_in, clk)
MemWrite_driver = random_signal(MemWrite_in, clk)
WB_driver = random_signal(WB_in, clk)
sim = Simulation(clock_driver, register_driver, ALU_driver, MemData_driver,
reg_driver, zero_driver, PC_driver, MemToReg_driver, MemWrite_driver,
WB_driver)
sim.run(MAX_CYCLES)
ID_Hazard_branch = Signal(intbv(0, 0, 2**1))
#create drivers for signals
reg_driver = traceSignals(
id_ex(clock, reset, ID_Hazard_lwstall, ID_Hazard_branch, branch_in,
MemRead_in, MemWrite_in, Jump_in, RegWrite_in, ALUSrc_in,
ALUOp_in, RegDst_in, MemToReg_in, jump_addr_in, PC_Plus4_in,
branch_addr_in, readA_in, readB_in, immi_sign_extended_in, RS_in,
RT_in, RD_in, funct_in, RegWrite_out, branch_out, MemRead_out,
MemWrite_out, Jump_out, ALUSrc_out, ALUOp_out, RegDst_out,
MemToReg_out, jump_addr_out, PC_Plus4_out, branch_addr_out,
readA_out, readB_out, immi_sign_extended_out, RS_out, RT_out,
RD_out, funct_out))
clock_driver = clock_generator(clock)
ID_Hazard_b_driver = random_signal(clock, ID_Hazard_branch)
ID_Hazard_lw_driver = random_signal(clock, ID_Hazard_lwstall)
branch_in_driver = random_signal(clock, branch_in)
MemRead_driver = random_signal(clock, MemRead_in)
MemWrite_driver = random_signal(clock, MemWrite_in)
Jump_driver = random_signal(clock, Jump_in)
RegWrite_driver = random_signal(clock, RegWrite_in)
ALUSrc_driver = random_signal(clock, ALUSrc_in)
ALUOp_driver = random_signal(clock, ALUOp_in)
RegDst_driver = random_signal(clock, RegDst_in)
MemToReg_driver = random_signal(clock, MemToReg_in)
jump_addr_driver = random_signal(clock, jump_addr_in)
PC_Plus4_driver = random_signal(clock, PC_Plus4_in)
branch_addr_driver = random_signal(clock, branch_addr_in)
readA_driver = random_signal(clock, readA_in)
readB_driver = random_signal(clock, readB_in)
#A test bench to send random signals to ALU make sure it's working correctly
from myhdl import *
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from ALU_Control import alu_control
if (__name__ == "__main__"):
#create signal variables
clk = Signal(intbv(0, 0, 2**1))
funct = Signal(intbv(0, 0, 2**6))
ALUop = Signal(intbv(0, 0, 2**3))
ALUcontrol = Signal(0)
#create drivers for the variables
clk_driver = clock_generator(clk)
funct_driver = random_signal(funct, clk)
ALUop_driver = random_signal(ALUop, clk)
ALU_driver = traceSignals(alu_control(ALUop, funct, ALUcontrol))
#run the simulation
sim = Simulation(clk_driver, funct_driver, ALUop_driver, ALU_driver)
sim.run(1000)
from myhdl import Signal, Simulation, intbv, traceSignals
from PC import program_counter
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
addr_out = Signal(intbv(0, 0, 2**32))
addr_in = Signal(intbv(0, 0, 2**32))
branch_signal = Signal(0)
clock = Signal(0)
pc_driver = traceSignals(
program_counter(clock, addr_out, addr_in, branch_signal))
clock_driver = clock_generator(clock)
rand_driver = random_signal(addr_in, clock)
pulse_driver = pulse_generator(clock, branch_signal)
sim = Simulation(clock_driver, rand_driver, pc_driver, pulse_driver)
sim.run(MAX_CYCLES)
from myhdl import Signal, Simulation, intbv, traceSignals
from Sign_Extender import Sign_Extender
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
instruction = Signal(intbv(0, 0, 2**32))
output = Signal(intbv(0, 0, 2**32))
clk = Signal(0)
pc_driver = traceSignals(Sign_Extender(clk, instruction, output))
clock_driver = clock_generator(clk)
rand_driver = random_signal(instruction, clk)
sim = Simulation(clock_driver, rand_driver, pc_driver)
sim.run(MAX_CYCLES)
MAX_CYCLES = 100000
#creates signal variables
BusA = Signal(intbv(0, 0, 2**32)) #output
BusB = Signal(intbv(0, 0, 2**32)) #output
BusW = Signal(intbv(0, 0, 2**32)) #input
RA = Signal(intbv(0, 0, 2**5)) #input
RB = Signal(intbv(0, 0, 2**5)) #input
RW = Signal(intbv(0, 0, 2**5)) #input
RegWr = Signal(intbv(0, 0, 2**1)) #input
clk = Signal(intbv(0, 0, 2**1)) #input
rst = Signal(0) #input
#makes an array for memory
outregs = []
for i in range(0, 32):
outregs.append(Signal(intbv(0, 0, 2**32)))
outregs[i].driven = not outregs[i].driven
#creates drivers for signals
busWAddress_driver = random_signal(clk, BusW)
readAAddress_driver = random_signal(clk, RA)
readBAddress_driver = random_signal(clk, RB)
readWAddress_driver = random_signal(clk, RW)
RegWr_driver = pulse_generator(clk, RegWr, delay=2)
reset_driver = pulse_generator(clk, rst, delay=40)
register_driver = traceSignals(
RegisterFile(BusA, BusB, BusW, RA, RB, RW, RegWr, clk, rst, outregs))
clock_driver = clock_generator(clk)
#create and run simulation
sim = Simulation(instances())
sim.run(MAX_CYCLES)
brFlush_in = Signal(intbv(0, 0, 2**1))
funct_in = Signal(intbv(0, 0, 2**6))
opCode_in = Signal(intbv(0, 0, 2**3))
clock = Signal(0)
reg_driver = traceSignals(
id_ex(clock, readA_in, readB_in, offset_in, PC_in, RTa_in, RTb_in,
RS_in, RD_in, WB_in, MemToReg_in, MemWrite_in, MemRead_in,
lwFlush_in, brFlush_in, funct_in, opCode_in, readA_out,
readB_out, offset_out, PC_out, RTa_out, RTb_out, RS_out, RD_out,
WB_out, MemToReg_out, MemWrite_out, MemRead_out, lwFlush_out,
brFlush_out, funct_out, opCode_out))
clock_driver = clock_generator(clock)
readA_driver = random_signal(readA_in, clock)
readB_driver = random_signal(readB_in, clock)
offset_driver = random_signal(offset_in, clock)
PC_driver = random_signal(PC_in, clock)
RTa_driver = random_signal(RTa_in, clock)
RTb_driver = random_signal(RTb_in, clock)
RS_driver = random_signal(RS_in, clock)
RD_driver = random_signal(RD_in, clock)
WB_driver = random_signal(WB_in, clock)
MemToReg_driver = random_signal(MemToReg_in, clock)
MemWrite_driver = random_signal(MemWrite_in, clock)
MemRead_driver = random_signal(MemRead_in, clock)
lwFlush_driver = random_signal(lwFlush_in, clock)
brFlush_driver = random_signal(brFlush_in, clock)
funct_driver = random_signal(funct_in, clock)
opCode_driver = random_signal(opCode_in, clock)
from myhdl import Signal, Simulation, intbv, traceSignals
from Instruction_Memory import Instruction_Memory
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Match_Test import match_test_report
from helpers.Paths import INDEX_256
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
test_file = INDEX_256
address = Signal(intbv(0, 0, 2**32))
out = Signal(intbv(0, 0, 2**32))
clk = Signal(0)
instruction_driver = traceSignals(
Instruction_Memory(clk, address, out, test_file))
clock_driver = clock_generator(clk)
rand_driver = random_signal(clk, address)
sim = Simulation(clock_driver, rand_driver, instruction_driver)
sim.run(MAX_CYCLES)
from IF_ID import if_id
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
if (__name__ == "__main__"):
MAX_CYCLES = 1000
clk = Signal(0)
inst_in = Signal(intbv(0, 0, 2**32))
inst_out = Signal(intbv(0, 0, 2**32))
PC_in = Signal(intbv(0, 0, 2**32))
PC_out = Signal(intbv(0, 0, 2**32))
IF_flush = Signal(0)
IFID_write = Signal(0)
rst = Signal(0)
clock_driver = clock_generator(clk, 10)
reg_driver = traceSignals(
if_id(clk, rst, inst_in, inst_out, PC_in, PC_out, IF_flush,
IFID_write))
inst_driver = random_signal(inst_in, clk)
PC_driver = random_signal(PC_in, clk)
IF_flush_driver = pulse_generator(clk, IF_flush, 20)
IFID_write_driver = pulse_generator(clk, IFID_write)
sim = Simulation(clock_driver, reg_driver, inst_driver, PC_driver,
IF_flush_driver, IFID_write_driver)
sim.run(MAX_CYCLES)
if (__name__ == "__main__"):
MAX_CYCLES = 100000
BusA = Signal(intbv(0, 0, 2**32)) #output
BusB = Signal(intbv(0, 0, 2**32)) #output
BusW = Signal(intbv(0, 0, 2**32)) #input
RA = Signal(intbv(0, 0, 2**5)) #input
RB = Signal(intbv(0, 0, 2**5)) #input
RW = Signal(intbv(0, 0, 2**5)) #input
RegWr = Signal(0) #input
clk = Signal(0) #input
rst = Signal(0) #input
outregs = []
for i in range(0, 32):
outregs.append(Signal(intbv(0, 0, 2**32)))
outregs[i].driven = not outregs[i].driven
busWAddress_driver = random_signal(BusW, clk)
readAAddress_driver = random_signal(RA, clk)
readBAddress_driver = random_signal(RB, clk)
readWAddress_driver = random_signal(RW, clk)
RegWr_driver = pulse_generator(clk, RegWr, delay=2)
reset_driver = pulse_generator(clk, rst, delay=40)
register_driver = traceSignals(
RegisterFile(BusA, BusB, BusW, RA, RB, RW, RegWr, clk, rst, outregs))
clock_driver = clock_generator(clk)
sim = Simulation(instances())
sim.run(MAX_CYCLES)
from myhdl import Signal, Simulation, intbv, traceSignals
from Data_Memory import Data_Memory
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from PC import program_counter
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 102800
clk = Signal(0)
address = Signal(intbv(0, 0, 2**32))
write = Signal(1)
readData = Signal(intbv(0, 0, 2**32))
writeData = Signal(intbv(0, 0, 2**32))
pc_driver = program_counter(clk, address, Signal(0), Signal(0))
writeData_driver = random_signal(writeData, clk)
dataMemory_driver = traceSignals(
Data_Memory(clk, address, write, readData, writeData))
clock_driver = clock_generator(clk)
sim = Simulation(pc_driver, clock_driver, dataMemory_driver,
writeData_driver)
sim.run(MAX_CYCLES)
from myhdl import *
from Control import *
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
if (__name__ == "__main__"):
clk = Signal(intbv(0, 0, 2**1))
opcode = Signal(intbv(0, 0, 2**6))
ALUSrc = Signal(intbv(0, 0, 2**1))
RegDst = Signal(intbv(0, 0, 2**2))
MemWrite = Signal(intbv(0, 0, 2**1))
MemRead = Signal(intbv(0, 0, 2**1))
Beq = Signal(intbv(0, 0, 2**1))
Jump = Signal(intbv(0, 0, 2**1))
MemToReg = Signal(intbv(0, 0, 2**2))
RegWrite = Signal(intbv(0, 0, 2**1))
ALUOp = Signal(intbv(0, 0, 2**3))
clk_driver = clock_generator(clk)
op_driver = random_signal(clk, opcode)
control_driver = traceSignals(
control(opcode, ALUSrc, RegDst, MemWrite, MemRead, Beq, Jump, MemToReg,
RegWrite, ALUOp))
sim = Simulation(clk_driver, control_driver, op_driver)
sim.run(1000)
RegWrite_in = Signal(0)
MemtoReg_in = Signal(intbv(0, 0, 2**2))
D_MEM_read_data_in = Signal(intbv(0, 0, 2**32))
D_MEM_read_addr_in = Signal(intbv(0, 0, 2**32))
EX_MEM_RegisterRd_in = Signal(intbv(0, 0, 2**5))
D_MEM_read_data_out = Signal(intbv(0, 0, 2**32))
D_MEM_read_addr_out = Signal(intbv(0, 0, 2**32))
MEM_WB_RegisterRd_out = Signal(intbv(0, 0, 2**5))
RegWrite_out = Signal(0)
MemtoReg_out = Signal(intbv(0, 0, 2**2))
rst = Signal(0)
clock_driver = clock_generator(clk, 10)
reg_driver = traceSignals(
mem_wb(clk, rst, RegWrite_in, MemtoReg_in, D_MEM_read_data_in,
D_MEM_read_addr_in, EX_MEM_RegisterRd_in, D_MEM_read_data_out,
D_MEM_read_addr_out, MEM_WB_RegisterRd_out, RegWrite_out,
MemtoReg_out))
MemtoReg_in_driver = random_signal(MemtoReg_in, clk)
D_MEM_read_data_in_driver = random_signal(D_MEM_read_data_in, clk)
D_MEM_read_addr_in_driver = random_signal(D_MEM_read_addr_in, clk)
EX_MEM_RegisterRd_in_driver = random_signal(EX_MEM_RegisterRd_in, clk)
RegWrite_in_driver = pulse_generator(clk, RegWrite_in, 20)
sim = Simulation(clock_driver, reg_driver, MemtoReg_in_driver,
D_MEM_read_data_in_driver, D_MEM_read_addr_in_driver,
EX_MEM_RegisterRd_in_driver, RegWrite_in_driver)
sim.run(MAX_CYCLES)
WB_in = Signal(intbv(0, 0, 2**1))
ALU_out = Signal(intbv(0, 0, 2**32))
MemData_out = Signal(intbv(0, 0, 2**32))
reg_out = Signal(intbv(0, 0, 2**5))
zero_out = Signal(intbv(0, 0, 2**1))
PC_out = Signal(intbv(0, 0, 2**32))
MemToReg_out = Signal(intbv(0, 0, 2**1))
MemWrite_out = Signal(intbv(0, 0, 2**1))
WB_out = Signal(intbv(0, 0, 2**1))
clock_driver = clock_generator(clk)
register_driver = traceSignals(
ex_mem(clk, ALU_in, ALU_out, MemData_in, MemData_out, reg_in, reg_out,
zero_in, zero_out, PC_in, PC_out, MemToReg_in, MemToReg_out,
MemWrite_in, MemWrite_out, WB_in, WB_out))
ALU_driver = random_signal(clk, ALU_in)
MemData_driver = random_signal(clk, MemData_in)
reg_driver = random_signal(clk, reg_in)
zero_driver = random_signal(clk, zero_in)
PC_driver = random_signal(clk, PC_in)
MemToReg_driver = random_signal(clk, MemToReg_in)
MemWrite_driver = random_signal(clk, MemWrite_in)
WB_driver = random_signal(clk, WB_in)
sim = Simulation(clock_driver, register_driver, ALU_driver, MemData_driver,
reg_driver, zero_driver, PC_driver, MemToReg_driver,
MemWrite_driver, WB_driver)
sim.run(MAX_CYCLES)
from myhdl import *
from Hazard_Detection_Unit import hazard_unit
from helpers.Random_Signal import random_signal
from helpers.Clock_Generator import clock_generator
if (__name__ == "__main__"):
#inputs
clk = Signal(intbv(0, 0, 2**1))
ID_EX_MemRead = Signal(intbv(0, 0, 2**1))
ID_EX_RegRt = Signal(intbv(0, 0, 2**2))
IF_ID_RegRs = Signal(intbv(0, 0, 2**2))
IF_ID_RegRt = Signal(intbv(0, 0, 2**2))
#outputs
Mux_Select_Stall = Signal(intbv(0, 0, 2**1))
PCWrite = Signal(intbv(0, 0, 2**1))
IF_ID_Write = Signal(intbv(0, 0, 2**1))
#drivers
clk_driver = clock_generator(clk)
ID_EX_MemRead_driver = random_signal(clk, ID_EX_MemRead)
ID_EX_RegRt_driver = random_signal(clk, ID_EX_RegRt)
IF_ID_RegRs_driver = random_signal(clk, IF_ID_RegRs)
IF_ID_RegRt_driver = random_signal(clk, IF_ID_RegRt)
HDU_driver = traceSignals(
hazard_unit(ID_EX_MemRead, ID_EX_RegRt, IF_ID_RegRs, IF_ID_RegRt,
Mux_Select_Stall, PCWrite, IF_ID_Write))
sim = Simulation(clk_driver, ID_EX_MemRead_driver, ID_EX_RegRt_driver,
IF_ID_RegRs_driver, IF_ID_RegRt_driver, HDU_driver)
sim.run(1000)
from myhdl import Signal, Simulation, intbv, traceSignals
from Instruction_Memory import Instruction_Memory
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
address = Signal(intbv(0, 0, 2**32))
out = Signal(intbv(0, 0, 2**32))
clk = Signal(0)
instruction_driver = traceSignals(Instruction_Memory(clk, address, out))
clock_driver = clock_generator(clk)
rand_driver = random_signal(address, clk)
sim = Simulation(clock_driver, rand_driver, instruction_driver)
sim.run(MAX_CYCLES)
from myhdl import *
from ALU import alu
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
if (__name__ == "__main__"):
clk = Signal(intbv(0, 0, 2**1))
reset = Signal(intbv(0, 0, 2**1))
readA = Signal(intbv(0, 0, 2**32))
readB = Signal(intbv(0, 0, 2**32))
CTRL = Signal(intbv(0, 0, 2**2))
R = Signal(intbv(0, 0, 2**32))
zero = Signal(intbv(0, 0, 2**1))
ovf = Signal(intbv(0, 0, 2**1))
clock_driver = clock_generator(clk)
ALUDriver = traceSignals(alu(clk, reset, readA, readB, CTRL, R, zero, ovf))
readADriver = random_signal(clk, readA)
readBDriver = random_signal(clk, readB)
CTRLDriver = random_signal(clk, CTRL)
sim = Simulation(instances())
sim.run(1000)
def run_RF_cosim():
# Initiate signals
MAX_TIME = 10000
clock = Signal(0)
reset = Signal(0, delay=10)
writeSignal = Signal(0, delay=10)
pyReadA = Signal(intbv(0, 0, 2**32))
pyReadB = Signal(intbv(0, 0, 2**32))
vReadA = Signal(intbv(0, 0, 2**32))
vReadB = Signal(intbv(0, 0, 2**32))
write = Signal(intbv(0, 0, 2**32), delay=10)
rAddrA = Signal(intbv(0, 0, 2**5))
rAddrB = Signal(intbv(0, 0, 2**5))
wAddr = Signal(intbv(0, 0, 2**5), delay=10)
pyregs = []
vregs = []
for i in range(0, 32):
pyregs.append(Signal(intbv(0, 0, 2**32)))
pyregs[i].driven = not pyregs[i].driven
vregs.append(Signal(intbv(0, 0, 2**32)))
vregs[i].driven = not vregs[i].driven
# Build driver instances
clock_driver = clock_generator(clock, period=20)
reset_driver = pulse_generator(clock, reset, delay=30)
write_driver = pulse_generator(clock, writeSignal, delay=2)
wd_rand = random_signal(clock, write, seed=1)
rdAddrA_rand = random_signal(clock, rAddrA, seed=2)
rdAddrB_rand = random_signal(clock, rAddrB, seed=3)
wAddr_rand = random_signal(clock, wAddr, seed=4)
py_cosim = traceSignals(
RegisterFile(pyReadA, pyReadB, write, rAddrA, rAddrB, wAddr,
writeSignal, clock, reset, pyregs))
v_cosim = v_rf(vReadA, vReadB, write, rAddrA, rAddrB, wAddr, writeSignal,
clock, reset, vregs)
read_test = match_test_report(clock, (vReadA, vReadB), (pyReadA, pyReadB),
a_name="v:",
b_name="py:")
reg_test = match_test_report(clock,
vregs,
pyregs,
a_name="verilog",
b_name="python")
sim = Simulation(instances())
inp = ""
help = 'Enter "run <cycles>" to run the simulation "print" to show the register files, or "quit" to exit.'
prompt = "command: "
print(help)
while (inp != "quit"):
inp = input(prompt)
if inp == "show":
for x, reg in enumerate(pyregs):
print("py[%d]=%#x" % (x, reg.val), end=' ')
print()
for x, reg in enumerate(vregs):
print(" v[%d]=%#x" % (x, reg.val), end=' ')
print()
if (pyregs == vregs):
print("They match")
else:
print("They don't match")
continue
elif inp.startswith("run "):
try:
cycles = int(inp.split()[1].strip())
sim.run(cycles)
continue
except ValueError:
pass
elif inp != "quit":
print(help)
from myhdl import Signal, Simulation, intbv, traceSignals
from Sign_Extender import Sign_Extender
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
instruction = Signal(intbv(0, 0, 2**16))
output = Signal(intbv(0, 0, 2**32))
clk = Signal(0)
pc_driver = traceSignals(Sign_Extender(instruction, output))
clock_driver = clock_generator(clk)
rand_driver = random_signal(clk, instruction)
sim = Simulation(clock_driver, rand_driver, pc_driver)
sim.run(MAX_CYCLES)
from myhdl import Signal, Simulation, intbv, traceSignals
from MUX import MUX
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
if (__name__ == "__main__"):
MAX_CYCLES = 1000
clk = Signal(0)
ctrl = Signal(0)
inputA = Signal(intbv(0, 0, 2**32))
inputB = Signal(intbv(0, 0, 2**32))
output = Signal(intbv(0, 0, 2**32))
clock_driver = clock_generator(clk)
ctrl_driver = pulse_generator(clk, ctrl)
inputA_driver = random_signal(inputA, clk)
inputB_driver = random_signal(inputB, clk)
MUX_driver = traceSignals(MUX(ctrl, inputA, inputB, output))
sim = Simulation(clock_driver, ctrl_driver, inputA_driver, inputB_driver,
MUX_driver)
sim.run(MAX_CYCLES)
from myhdl import *
from Multiplexers import *
from helpers.Pulse_Generator import pulse_generator
from helpers.Random_Signal import random_signal
from helpers.Clock_Generator import clock_generator
if (__name__ == "__main__"):
clk = Signal(intbv(0, 0, 2**1))
ctrl = Signal(intbv(0, 0, 2**2))
input1 = Signal(intbv(0, 0, 2**32))
input2 = Signal(intbv(0, 0, 2**32))
input3 = Signal(intbv(0, 0, 2**32))
output = Signal(intbv(0, 0, 2**32))
clk_driver = clock_generator(clk)
ctrl_driver = random_signal(ctrl, clk)
input1_driver = random_signal(input1, clk)
input2_driver = random_signal(input2, clk)
input3_driver = random_signal(input3, clk)
def instances():
#MUX1_driver = traceSignals(first_alu_mux_3_to_1(input1, input2, input3, ctrl, output))
#MUX2_driver = traceSignals(second_alu_mux_3_to_1(input1, input2, input3, ctrl, output))
#MUX3_driver = traceSignals(third_alu_mux_2_to_1(input1, input2, ctrl, output))
#MUX4_driver = traceSignals(idEx_to_exMem_mux_2_to_1(input1, input2, ctrl, output))
#MUX5_driver = traceSignals(writeback_source_mux_3_to_1(input1, input2, input3, ctrl, output))
#MUX6_driver = traceSignals(regDst_mux_3_to_1(input1, input2, input3, ctrl, output))
#MUX7_driver = traceSignals(first_jump_or_branch_mux_2_to_1(input1, input2, ctrl, output))
#MUX8_driver = traceSignals(second_jump_or_branch_mux_2_to_1(input1, input2, ctrl, output))
#MUX9_driver = traceSignals(third_jump_or_branch_mux_2_to_1(input1, input2, ctrl, output))
MUXX_driver = traceSignals(
from myhdl import *
from branch_jump_calc import *
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
if (__name__ == "__main__"):
#create signal variables
clk = Signal(intbv(0, 0, 2**1))
In1_instruction = Signal(intbv(0, 0, 2**16))
In2_pc_plus_4 = Signal(intbv(0, 0, 2**32))
Jump_Address = Signal(intbv(0, 0, 2**32))
bta_Address = Signal(intbv(0, 0, 2**32))
#create drivers for signals
clk_driver = clock_generator(clk)
In1_instruction_driver = random_signal(In1_instruction, clk)
In2_pc_plus_4_driver = random_signal(In2_pc_plus_4, clk)
bta = branch_calculator(In1_instruction, In2_pc_plus_4, Jump_Address)
jump = jump_calculator(In1_instruction, In2_pc_plus_4, bta_Address)
driver = traceSignals(bta)
#NOTE: to switch between jump and branch calc just change jump_calculator to branch_calculator
#then run Simulation
sim = Simulation(clk_driver, In1_instruction_driver, In2_pc_plus_4_driver,
driver)
sim.run(1000)
from myhdl import Signal, Simulation, intbv, traceSignals
from PC import program_counter
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from helpers.Pulse_Generator import pulse_generator
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 1000
addr_out = Signal(intbv(0, 0, 2**32))
addr_in = Signal(intbv(0, 0, 2**32))
branch_signal = Signal(0)
clock = Signal(0)
pc_driver = traceSignals(
program_counter(clock, addr_out, addr_in, branch_signal))
clock_driver = clock_generator(clock)
rand_driver = random_signal(clock, addr_in)
pulse_driver = pulse_generator(clock, branch_signal)
sim = Simulation(clock_driver, rand_driver, pc_driver, pulse_driver)
sim.run(MAX_CYCLES)
from myhdl import Signal, Simulation, intbv, traceSignals
from Data_Memory import Data_Memory
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
from PC import program_counter
# Program Counter Testbench
# Runs the PC for max_cycles
# Gives the branch signal and a new address every 10 cycles
if (__name__ == "__main__"):
MAX_CYCLES = 102800
clk = Signal(0)
address = Signal(intbv(0, 0, 2**32))
write = Signal(1)
readData = Signal(intbv(0, 0, 2**32))
writeData = Signal(intbv(0, 0, 2**32))
pc_driver = program_counter(clk, address, Signal(0), Signal(0))
writeData_driver = random_signal(clk, writeData)
dataMemory_driver = traceSignals(
Data_Memory(clk, address, write, readData, writeData))
clock_driver = clock_generator(clk)
sim = Simulation(pc_driver, clock_driver, dataMemory_driver,
writeData_driver)
sim.run(MAX_CYCLES)
from myhdl import *
from ALU import alu
from helpers.Clock_Generator import clock_generator
from helpers.Random_Signal import random_signal
if (__name__ == "__main__"):
clk = Signal(intbv(0, 0, 2**1))
reset = Signal(intbv(0, 0, 2**1))
readA = Signal(intbv(0, 0, 2**32))
readB = Signal(intbv(0, 0, 2**32))
CTRL = Signal(intbv(0, 0, 2**2))
R = Signal(intbv(0, 0, 2**32))
zero = Signal(intbv(0, 0, 2**1))
ovf = Signal(intbv(0, 0, 2**1))
clock_driver = clock_generator(clk)
ALUDriver = traceSignals(alu(clk, reset, readA, readB, CTRL, R, zero, ovf))
readADriver = random_signal(readA, clk)
readBDriver = random_signal(readB, clk)
CTRLDriver = random_signal(CTRL, clk)
sim = Simulation(instances())
sim.run(1000)
