def synthesize(aiger_spec: str, is_moore: bool,
bad_out_name: str) -> str or None:
aiger_file = create_unique_file(aiger_spec)
logging.debug("synthesize: using %s to store aiger_spec" % aiger_file)
logging.info('executing sdf...')
rc, out, err = execute_shell('{sdf} {aiger_file} -f {is_moore}'.format(
sdf=SDF_PATH,
aiger_file=aiger_file,
is_moore='-moore' if is_moore else ''))
assert is_empty_str(err), rc_out_err_to_str(rc, out, err)
assert rc in (REALIZABLE_RC,
UNREALIZABLE_RC), rc_out_err_to_str(rc, out, err)
logging.info('sdf completed')
logging.debug('sdf returned:\n' + out)
out_split = out.splitlines()
status = out_split[0]
if status == REALIZABLE_STR:
full_model = convert_aiger_model_to_tlsf_model(
'\n'.join(out_split[1:]), bad_out_name)
os.remove(aiger_file)
return full_model
os.remove(aiger_file)
return None
def _run_benchmark(solver:str, is_real:bool, bench_file_name:str, mc:bool) -> str or None:
str_by_rc = {R_RC:'real_rc', U_RC:'unreal_rc', UNKN_RC:'unknown_rc'}
rc, out, err = execute_shell('{solver} {bench}'.format(solver=solver, bench=bench_file_name))
if rc not in (U_RC, R_RC, UNKN_RC):
return rc_out_err_to_str(rc, out, err)
exp_rc = (U_RC, R_RC)[is_real]
if exp_rc != rc:
return 'Realizability differs (expected vs. actual): %s vs. %s'\
% (str_by_rc[exp_rc], str_by_rc[rc])
out_lines = out.splitlines()
if (is_real and out_lines[0] != R_STR) or (not is_real and out_lines[0] != U_STR):
return 'stdout first line should be %s, got instead: %s'\
% ((U_STR, R_STR)[is_real], out_lines[0])
if not mc or not is_real:
return None
aiger_solution = '\n'.join(out_lines[1:])
aiger_solution_file_name = create_unique_file(aiger_solution)
is_correct = check_model.main(aiger_solution_file_name, bench_file_name, False)
if not is_correct:
return "the model is wrong"
os.remove(aiger_solution_file_name)
return None
def _create_monitor_file(tlsf_file_name) -> str:
rc, out, err = execute_shell('{syfco} -f smv {tlsf_file} -m fully'.format(
syfco=SYFCO_PATH, tlsf_file=tlsf_file_name))
assert_exec_strict(rc, out, err)
rc, out, err = execute_shell('{smvtoaig} -a -L "{ltl2smv}"'.format(
smvtoaig=SMVTOAIG_PATH, ltl2smv=LTL2SMV_PATH),
input=out)
assert rc == 0, rc_out_err_to_str(rc, out,
err) # it outputs the LTL into stderr
return create_unique_file(out, suffix='.aag')
def _model_check(combined_aiger_file: str) -> int:
""" :return: 0 if correct, 1 if wrong """
for pi in range(get_nof_properties(combined_aiger_file)):
logging.debug('checking property ' + str(pi))
rc, out, err = execute_shell('{IIMC} {aiger_file} --pi {pi}'.format(
IIMC=IIMC_PATH, aiger_file=combined_aiger_file, pi=pi))
assert rc == 0, 'model checking call failed: \n' + rc_out_err_to_str(
rc, out, err)
is_correct = out.splitlines()[0].strip() == '0'
if not is_correct:
return 1
# end of for
return 0
def _create_monitor_file(tlsf_file_name) -> str:
rc, out, err = execute_shell('{syfco} -f smv {tlsf_file} -m fully'.format(syfco=SYFCO_PATH,
tlsf_file=tlsf_file_name))
assert_exec_strict(rc, out, err)
rc, out, err = execute_shell('{smvtoaig} -a'.format(smvtoaig=SMVTOAIG_PATH), input=out)
assert rc == 0, rc_out_err_to_str(rc, out, err) # it outputs the LTL into stderr
(fd, aag_file_name) = tempfile.mkstemp(text=True, suffix='.aag')
os.write(fd, bytes(out, encoding=sys.getdefaultencoding()))
os.close(fd)
return aag_file_name
def _model_check(combined_aiger_file:str) -> int:
""" :return: 0 if correct, 1 if wrong """
for pi in range(get_nof_properties(combined_aiger_file)):
logging.debug('checking property ' + str(pi))
rc, out, err = execute_shell('{IIMC} {aiger_file} --pi {pi}'.format(
IIMC=IIMC_PATH,
aiger_file=combined_aiger_file,
pi=pi))
assert rc == 0, 'model checking call failed: \n' + rc_out_err_to_str(rc, out, err)
is_correct = out.splitlines()[0].strip() == '0'
if not is_correct:
return 1
return 0
def verilog_to_aiger(verilog:str) -> str:
input_verilog_file = create_tmp_file(verilog, suffix='v')
file_blif_mv = create_tmp_file(suffix='.mv')
file_aiger_tmp = create_tmp_file(suffix='.aag')
file_output_aiger = create_tmp_file(suffix='.aag')
files_to_remove = (input_verilog_file,
file_blif_mv,
file_aiger_tmp,
file_output_aiger) # tmp files stay if smth goes wrong
# vl2mv
# on some examples vl2mv fails with a standard stack limit, so we raise it
hard_limit = resource.getrlimit(resource.RLIMIT_STACK)[1]
resource.setrlimit(resource.RLIMIT_STACK, (hard_limit, hard_limit))
rc, out, err = execute_shell('{vl2mv} {file_input_verilog} -o {file_blif_mv}'.format(
vl2mv=VL2MV_PATH,
file_input_verilog=input_verilog_file,
file_blif_mv=file_blif_mv))
if rc == -11:
logging.warning('vl2mv caught SIGSEGV: ha-ha! Re-run me on this example, or manually convert into aiger')
logging.debug('verilog was: ' + readfile(input_verilog_file))
assert rc == 0, rc_out_err_to_str(rc, out, err) # no check that stderr='' because vl2mv outputs the input file name
# abc
rc, out, err = execute_shell('{abc} -c '
'"read_blif_mv {file_blif_mv}; '
'strash; refactor; rewrite; dfraig; rewrite; dfraig; '
'write_aiger -s {file_aiger_tmp}"'.format(
file_blif_mv=file_blif_mv,
abc=ABC_PATH,
file_aiger_tmp=file_aiger_tmp))
assert_exec_strict(rc, out, err)
# aigtoaig
rc, out, err = execute_shell('{aigtoaig} {file_aiger_tmp} {file_output_aiger}'.format(
aigtoaig=AIGTOAIG_PATH,
file_aiger_tmp=file_aiger_tmp,
file_output_aiger=file_output_aiger))
assert_exec_strict(rc, out, err)
res = readfile(file_output_aiger)
[os.remove(f) for f in files_to_remove]
return res
