def test_downto(self):
a = self.n.sig('a', dtype=INT)
a.defVal = hInt(10)
b = hInt(0)
r = a._downto(b)
res = r.staticEval()
self.assertEqual(res.val[0].val, 10)
self.assertEqual(res.val[1].val, 0)
def test_DivInt(self):
v8 = hInt(8)
v4 = hInt(4)
v2 = hInt(2)
self.assertValEq(v8 // v4, 2)
self.assertValEq(v8 // v2, 4)
self.assertValEq(v4 // v2, 2)
def test_DivInt(self):
v8 = hInt(8)
v4 = hInt(4)
v2 = hInt(2)
self.assertValEq(v8 // v4, 2)
self.assertValEq(v8 // v2, 4)
self.assertValEq(v4 // v2, 2)
def test_downto(self):
a = self.n.sig('a', dtype=INT)
a.defVal = hInt(10)
b = hInt(0)
r = a._downto(b)
res = r.staticEval()
self.assertEqual(res.val[0].val, 10)
self.assertEqual(res.val[1].val, 0)
def test_AddInt(self):
v0 = hInt(0)
v1 = hInt(1)
v5 = hInt(5)
self.assertValEq(v0 + v1, 1)
self.assertValEq(v1 + v5, 6)
self.assertValEq(v0 + v1 + v5, 6)
self.assertValEq(v1 + hInt(1), 2)
def test_AddInt(self):
v0 = hInt(0)
v1 = hInt(1)
v5 = hInt(5)
self.assertValEq(v0 + v1, 1)
self.assertValEq(v1 + v5, 6)
self.assertValEq(v0 + v1 + v5, 6)
self.assertValEq(v1 + hInt(1), 2)
def test_BitsIndexTypes(self):
t = Bits(8)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v[object()]
with self.assertRaises(IndexError):
v[9:]
with self.assertRaises(IndexError):
v[:-1]
p = Param(2)
self.assertIsInstance(v[p], RtlSignalBase)
self.assertEqual(v[p]._dtype.bit_length(), 1)
p2 = p._downto(0)
self.assertIsInstance(v[p2], RtlSignalBase)
self.assertEqual(v[p2]._dtype.bit_length(), 2)
p3 = Param("abc")
with self.assertRaises(TypeError):
v[p3]
a = RtlSignal(None, "a", BIT)
a._const = False
with self.assertRaises(TypeError):
v[p] = a
with self.assertRaises(TypeError):
v[a] = p
v[p] = 1
self.assertEqual(v, 5)
v[p2] = 2
self.assertEqual(v, 6)
with self.assertRaises(TypeError):
v[hInt(None)] = 2
v[:] = 0
self.assertEqual(v, 0)
v[2] = 1
self.assertEqual(v, 4)
v[3:] = p
self.assertEqual(v, 2)
v._setitem__val(hInt(None), hInt(1))
with self.assertRaises(ValueError):
int(v)
with self.assertRaises(TypeError):
v[hStr("asfs")]
def test_BitsIndexTypes(self):
t = Bits(8)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v[object()]
with self.assertRaises(IndexError):
v[9:]
with self.assertRaises(IndexError):
v[:-1]
p = Param(2)
self.assertIsInstance(v[p], RtlSignalBase)
self.assertEqual(v[p]._dtype.bit_length(), 1)
p2 = p._downto(0)
self.assertIsInstance(v[p2], RtlSignalBase)
self.assertEqual(v[p2]._dtype.bit_length(), 2)
p3 = Param("abc")
with self.assertRaises(TypeError):
v[p3]
a = RtlSignal(None, "a", BIT)
a._const = False
with self.assertRaises(TypeError):
v[p] = a
with self.assertRaises(TypeError):
v[a] = p
v[p] = 1
self.assertEqual(v, 5)
v[p2] = 2
self.assertEqual(v, 6)
with self.assertRaises(TypeError):
v[hInt(None)] = 2
v[:] = 0
self.assertEqual(v, 0)
v[2] = 1
self.assertEqual(v, 4)
v[3:] = p
self.assertEqual(v, 2)
v._setitem__val(hInt(None), hInt(1))
with self.assertRaises(ValueError):
int(v)
with self.assertRaises(TypeError):
v[hStr("asfs")]
def test_ADD_eval(self):
for a_in, b_in, out in [(0, 0, 0), (0, 1, 1), (1, 0, 1), (1, 1, 2)]:
res = hInt(a_in) + hInt(b_in)
b_w = 2
self.assertTrue(res.vldMask)
self.assertEqual(res.val, out,
"a_in %d, b_in %d, out %d" % (a_in, b_in, out))
resBit = vec(a_in, b_w) + vec(b_in, b_w)
self.assertEqual(resBit.vldMask, 3)
self.assertEqual(resBit.val, out,
"a_in %d, b_in %d, out %d" % (a_in, b_in, out))
def serialzeValueToTCL(self, val, do_eval=False) -> Tuple[str, str, bool]:
"""
:see: doc of method on parent class
"""
if isinstance(val, int):
val = hInt(val)
if do_eval:
val = val.staticEval()
buff = StringIO()
to_hdl = ToHdlAstVivadoTclExpr()
ser = Vhdl2008Serializer.TO_HDL(buff)
hdl = to_hdl.as_hdl(val)
ser.visit_iHdlObj(hdl)
tclVal = buff.getvalue()
if isinstance(val, RtlSignalBase):
buff = StringIO()
hdl = to_hdl.as_hdl(val.staticEval())
ser = Vhdl2008Serializer.TO_HDL(buff)
ser.visit_iHdlObj(hdl)
tclValVal = buff.getvalue()
return tclVal, tclValVal, False
else:
return tclVal, tclVal, True
def serialzeValueToTCL(self, val, do_eval=False) -> Tuple[str, str, bool]:
"""
:see: doc of method on parent class
"""
if isinstance(val, int):
val = hInt(val)
if do_eval:
val = val.staticEval()
buff = StringIO()
def createTmpVar(suggestedName, dtype):
raise NotImplementedError(
f"Width value can not be converted do ipcore format ({val})")
to_hdl = ToHdlAstVivadoTclExpr()
to_hdl.createTmpVarFn = createTmpVar
ser = Vhdl2008Serializer.TO_HDL(buff)
hdl = to_hdl.as_hdl(val)
ser.visit_iHdlObj(hdl)
tclVal = buff.getvalue()
if isinstance(val, RtlSignalBase):
buff = StringIO()
hdl = to_hdl.as_hdl(val.staticEval())
ser = Vhdl2008Serializer.TO_HDL(buff)
ser.visit_iHdlObj(hdl)
tclValVal = buff.getvalue()
return tclVal, tclValVal, False
else:
return tclVal, tclVal, True
def __setitem__(self, index, value):
"""
this []= operator can not be called in desing description, it can be only used to update HValues
"""
if not isinstance(self, HValue):
raise TypeError(
"To assign a member of hdl arrray/vector/list/... use a[index](val) instead of a[index] = val"
)
# convert index to hSlice or hInt
if isinstance(index, HValue):
index = index
elif isinstance(index, slice):
length = self._dtype.bit_length()
index = slice_to_SLICE(index, length)
if not index._is_full_valid():
raise ValueError("invalid index", index)
else:
index = hInt(index)
# convert value to bits of length specified by index
if index._dtype == SLICE:
Bits = self._dtype.__class__
itemT = Bits(index._size())
else:
itemT = BIT
if isinstance(value, HValue):
value = value._auto_cast(itemT)
else:
value = itemT.from_py(value)
return Bits3val.__setitem__(self, index, value)
def getVectorFromType(self, dtype) -> Union[bool, None, Tuple[int, int]]:
"""
:see: doc of method on parent class
"""
if dtype == BIT:
return False
elif isinstance(dtype, Bits):
return [dtype.bit_length() - 1, hInt(0)]
def test_BitsConcatIncompatibleType(self):
t = Bits(1)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v._concat(hInt(2))
p = Param(1)
with self.assertRaises(TypeError):
v._concat(p)
def test_BitsConcatIncompatibleType(self):
t = Bits(1)
v = t.fromPy(1)
with self.assertRaises(TypeError):
v._concat(hInt(2))
p = Param(1)
with self.assertRaises(TypeError):
v._concat(p)
def test_ADD_eval(self):
for a_in, b_in, out in [(0, 0, 0),
(0, 1, 1),
(1, 0, 1),
(1, 1, 2)]:
res = hInt(a_in) + hInt(b_in)
b_w = 2
self.assertTrue(res.vldMask)
self.assertEqual(
res.val, out,
"a_in %d, b_in %d, out %d"
% (a_in, b_in, out))
resBit = vec(a_in, b_w) + vec(b_in, b_w)
self.assertEqual(resBit.vldMask, 3)
self.assertEqual(
resBit.val, out,
"a_in %d, b_in %d, out %d"
% (a_in, b_in, out))
def __setitem__(self, index, value):
"""
this can not be called in desing description on non static values,
only simulator can resolve this (in design use self[index] ** value
instead of self[index] = value)
"""
# convert index to hSlice or hInt
indexConst = True
if not isinstance(index, Value):
if isinstance(index, RtlSignalBase):
if index._const:
index = index.staticEval()
else:
indexConst = False
elif isinstance(index, slice):
length = self._dtype.bit_length()
index = slice_to_SLICE(index, length)
else:
index = hInt(index)
if indexConst and not index._is_full_valid():
indexConst = False
# convert value to bits of length specified by index
if indexConst:
if index._dtype == SLICE:
Bits = self._dtype.__class__
itemT = Bits(index._size())
else:
itemT = BIT
if not isinstance(value, Value):
if isinstance(value, RtlSignalBase):
if value._const:
value = value.staticEval()._auto_cast(itemT)
valueConst = True
else:
valueConst = False
else:
value = itemT.from_py(value)
valueConst = True
else:
valueConst = True
value = value._auto_cast(itemT)
if indexConst and valueConst and isinstance(self, Value):
return Bits3val.__setitem__(self, index, value)
raise TypeError(
"Only simulator can resolve []= for signals or invalid index")
def log2ceil(x):
"""
Returns no of bits required to store x-1
for example x=8 returns 3
"""
if not isinstance(x, (int, float)):
x = int(x)
if x == 0 or x == 1:
res = 1
else:
res = math.ceil(math.log2(x))
return hInt(res)
def test_ADD_IntBits(self):
a = vec(7, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
a = vec(7, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
def test_ADD_IntBits(self):
a = vec(7, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
a = vec(7, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 8)
self.assertEqual(c.vldMask, mask(8))
a = vec(255, 8, False)
b = hInt(1)
c = a + b
self.assertEqual(c.val, 0)
self.assertEqual(c.vldMask, mask(8))
def mkBoundry(name, val):
if isinstance(val, int):
val = hInt(val)
d = appendSpiElem(v, name)
d.attrib["spirit:format"] = "long"
if isinstance(val, RtlSignalBase):
# value is simple type and does not contains generic etc...
resolve = 'dependent'
d.attrib["spirit:dependency"] = "(%s)" %\
VivadoTclExpressionSerializer.asHdl(val)
d.text = VivadoTclExpressionSerializer.asHdl(
val.staticEval())
else:
resolve = "immediate"
d.text = VivadoTclExpressionSerializer.asHdl(val, None)
d.attrib["spirit:resolve"] = resolve
def serialzeValueToTCL(self, val, do_eval=False) -> Tuple[str, str, bool]:
"""
:see: doc of method on parent class
"""
if isinstance(val, int):
val = hInt(val)
if do_eval:
val = val.staticEval()
if isinstance(val, RtlSignalBase):
ctx = VivadoTclExpressionSerializer.getBaseContext()
tclVal = VivadoTclExpressionSerializer.asHdl(val, ctx)
tclValVal = VivadoTclExpressionSerializer.asHdl(
val.staticEval())
return tclVal, tclValVal, False
else:
tclVal = VivadoTclExpressionSerializer.asHdl(val, None)
return tclVal, tclVal, True
def _entPort2CompPort(e, p):
port = Port()
port.name = p.name
port.direction = p.direction.name.lower()
port.type = WireTypeDef()
t = port.type
dt = p._dtype
t.typeName = VhdlSerializer.HdlType(dt,
VhdlSerializer.getBaseContext())
try:
t.typeName = t.typeName[:t.typeName.index('(')]
except ValueError:
pass
if dt == BIT:
port.vector = False
elif isinstance(dt, Bits):
port.vector = [evalParam(dt.width) - 1, hInt(0)]
t.viewNameRefs = [
"xilinx_vhdlsynthesis", "xilinx_vhdlbehavioralsimulation"
]
return port
def HdlType_bits(cls, typ, ctx, declaration=False):
disableRange = False
bitLength = typ.bit_length()
w = typ.width
isVector = typ.forceVector or bitLength > 1
if typ.signed is None:
if isVector:
name = 'STD_LOGIC_VECTOR'
else:
return 'STD_LOGIC'
elif typ.signed:
name = "SIGNED"
else:
name = 'UNSIGNED'
if disableRange:
constr = ""
elif isinstance(w, int):
constr = "(%d DOWNTO 0)" % (w - 1)
else:
o = Operator(AllOps.SUB, (w, hInt(1)))
constr = "(%s DOWNTO 0)" % cls.Operator(o, ctx)
return name + constr
def _config(self):
self.SIZE = hInt(3)
Axi4Lite._config(self)
def _config(self):
self.DATA_WIDTH = Param(8)
self.LEN = hInt(3)
def _config(self):
self.DATA_WIDTH = Param(8)
self.LEN = hInt(3)
def _config(self):
self.SIZE = hInt(3)
Axi4Lite._config(self)
