def _declr(self): addClkRstn(self) INTF_CLS = self.intfCls INPUT_CNT = self.INPUT_CNT OUTPUT_CNT = len(self.OUTPUTS) self.OUTS_FOR_IN = self._masters_for_slave(self.OUTPUTS, self.INPUT_CNT) with self._paramsShared(): self.dataIn = HObjList([INTF_CLS() for _ in range(INPUT_CNT)]) with self._paramsShared(): self.dataOut = HObjList( [INTF_CLS()._m() for _ in range(OUTPUT_CNT)]) # master index for each slave so slave knows # which master did read and where is should send it order_dout_index_for_din_in = HObjList() for connected_outs in self.OUTS_FOR_IN: if len(connected_outs) > 1: f = Handshaked() f.DATA_WIDTH = log2ceil(OUTPUT_CNT) else: f = None order_dout_index_for_din_in.append(f) self.order_dout_index_for_din_in = order_dout_index_for_din_in order_din_index_for_dout_in = HObjList() # slave index for each master # so master knows where it should expect the data for connected_ins in self.OUTPUTS: if len(connected_ins) > 1: f = Handshaked() f.DATA_WIDTH = log2ceil(INPUT_CNT) else: f = None order_din_index_for_dout_in.append(f) self.order_din_index_for_dout_in = order_din_index_for_dout_in
def _declr(self): with self._paramsShared(): # user requests self.req = AddrSizeHs() with self._paramsShared(exclude=({"ID_WIDTH"}, set())): self.w = AxiStream() if self.ID_WIDTH: ack = Handshaked(masterDir=DIRECTION.IN) ack.DATA_WIDTH = self.ID_WIDTH else: ack = HandshakeSync(masterDir=DIRECTION.IN) self.ack = ack