class EpWithReg(Unit):
"""
Unit with AxiLiteEndpoint and AxiLiteReg together
"""
def __init__(self, structTemplate, intfCls=Axi4Lite, shouldEnterFn=None):
BusEndpoint.__init__(self,
structTemplate,
intfCls=intfCls,
shouldEnterFn=shouldEnterFn)
def _config(self):
BusEndpoint._config(self)
def _mkFieldInterface(self, structIntf, field):
return BusEndpoint._mkFieldInterface(self, structIntf, field)
@staticmethod
def _defaultShouldEnterFn(field):
return BusEndpoint._defaultShouldEnterFn(field)
def _declr(self):
BusEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
self.reg = AxiLiteReg(self._intfCls)
def _impl(self):
propagateClkRstn(self)
self.decoded(self.ep.decoded)
self.reg.in_s(self.bus)
self.ep.bus(self.reg.out_m)
class AxiLiteEndpointBehindStaticRemap(Unit):
def _config(self):
self.MEM_MAP = Param([])
def __init__(self,
structTemplate,
intfCls=Axi4Lite,
shouldEnterFn=BusEndpoint._defaultShouldEnterFn):
BusEndpoint.__init__(self,
structTemplate,
intfCls=intfCls,
shouldEnterFn=shouldEnterFn)
def _mkFieldInterface(self, structIntf: StructIntf, field: HStructField):
return BusEndpoint._mkFieldInterface(self, structIntf, field)
def _declr(self):
AxiLiteEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
self.remap = AxiStaticRemap(Axi4Lite)
def _impl(self):
self.remap.s(self.bus)
self.ep.bus(self.remap.m)
self.decoded(self.ep.decoded)
propagateClkRstn(self)
class AxiLiteEpWithReg(Unit):
"""
:class:`hwt.synthesizer.unit.Unit` with AxiLiteEndpoint and AxiLiteReg together
"""
def __init__(self, structTemplate, intfCls=Axi4Lite, shouldEnterFn=None):
BusEndpoint.__init__(self,
structTemplate,
intfCls=intfCls,
shouldEnterFn=shouldEnterFn)
def _config(self):
BusEndpoint._config(self)
def _mkFieldInterface(self, structIntf: StructIntf, field: HStructField):
return BusEndpoint._mkFieldInterface(self, structIntf, field)
@staticmethod
def _defaultShouldEnterFn(root, field_path):
return BusEndpoint._defaultShouldEnterFn(root, field_path)
def _declr(self):
BusEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
def _impl(self):
propagateClkRstn(self)
self.decoded(self.ep.decoded)
m = AxiBuilder(self, self.bus).buff(addr_items=1, data_items=1).end
self.ep.bus(m)
class EpWithReg(Unit):
"""
Unit with AxiLiteEndpoint and AxiLiteReg together
"""
def __init__(self, structTemplate, intfCls=Axi4Lite, shouldEnterFn=None):
BusEndpoint.__init__(self, structTemplate,
intfCls=intfCls,
shouldEnterFn=shouldEnterFn)
def _config(self):
BusEndpoint._config(self)
def _mkFieldInterface(self, structIntf, field):
return BusEndpoint._mkFieldInterface(self, structIntf, field)
@staticmethod
def _defaultShouldEnterFn(field):
return BusEndpoint._defaultShouldEnterFn(field)
def _declr(self):
BusEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
self.reg = AxiLiteReg(self._intfCls)
def _impl(self):
propagateClkRstn(self)
self.decoded(self.ep.decoded)
self.reg.in_s(self.bus)
self.ep.bus(self.reg.out_m)
def mySetUp(self, data_width=32):
u = AxiLiteEndpoint(self.STRUCT_TEMPLATE,
shouldEnterFn=lambda root, field_path:\
(True, isinstance(field_path_get_type(root, field_path), Bits)))
self.u = u
self.DATA_WIDTH = data_width
u.DATA_WIDTH = self.DATA_WIDTH
self.compileSimAndStart(self.u, onAfterToRtl=self.mkRegisterMap)
return u
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axis_out = AxiStream()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = Axi4Lite()
reg_t = Bits(self.CNTRL_DATA_WIDTH)
self.conv = AxiLiteEndpoint(
HStruct((reg_t, "enable"), (reg_t, "len")))
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axi = Axi4Lite()
with self._paramsShared():
# this structure is configuration of interfaces
# fields can also be arrays and metaclass can be used
# to specify field interface and R/W access to field
self.conv = AxiLiteEndpoint(
HStruct((uint32_t, "reg0"),
(uint32_t, "reg1")
))
class AxisFrameGen(Unit):
"""
Generator of axi stream frames for testing purposes
.. hwt-schematic::
"""
def _config(self):
self.MAX_LEN = Param(511)
self.CNTRL_ADDR_WIDTH = Param(4)
self.CNTRL_DATA_WIDTH = Param(32)
self.DATA_WIDTH = Param(64)
self.USE_STRB = Param(True)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axis_out = AxiStream()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = Axi4Lite()
reg_t = Bits(self.CNTRL_DATA_WIDTH)
self.conv = AxiLiteEndpoint(
HStruct((reg_t, "enable"), (reg_t, "len")))
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld, connect(cEn.dout.data, en, fit=True))
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld, connect(cLen.dout.data, _len, fit=True))
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld, connect(cLen.dout.data, cntr, fit=True)).Else(
If(out.ready & en,
If(cntr._eq(0), cntr(_len)).Else(cntr(cntr - 1))))
def _impl(self):
self.signalLoop.din(self.signalIn)
self.regCntrlOut(self.regCntrlLoop.dout)
self.vldSyncedOut(self.vldSyncedLoop.dout)
self.bramOut(self.bramLoop.dout)
def configEp(ep):
ep._updateParamsFrom(self)
rltSig10 = self._sig("sig", Bits(self.DATA_WIDTH), defVal=10)
interfaceMap = IntfMap([
(rltSig10, "rltSig10"),
(self.signalLoop.dout, "signal"),
(self.regCntrlLoop.din, "regCntrl"),
(self.vldSyncedLoop.din, "vldSynced"),
(self.bramLoop.din, "bram"),
(Bits(self.DATA_WIDTH), None),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
axiLiteConv.decoded.vldSynced.din(None)
propagateClkRstn(self)
def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH = 16
en0 = AxiS_en()
en0.USE_STRB = True
en0.USE_KEEP = True
en0.ID_WIDTH = 8
en0.DEST_WIDTH = 4
en0.USER_WIDTH = 12
u0 = SimpleUnitWithParam()
u0.DATA_WIDTH = 2
u1 = SimpleUnitWithParam()
u1.DATA_WIDTH = 3
u_with_hdl_params = MultiConfigUnitWrapper([u0, u1])
testUnits = [
AxiS_en(),
en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(),
f,
Axi4streamToMem(),
IpCoreIntfTest(),
u_with_hdl_params,
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def _impl(self):
self.signalLoop.din(self.signalIn)
self.regCntrlOut(self.regCntrlLoop.dout)
self.vldSyncedOut(self.vldSyncedLoop.dout)
self.bramOut(self.bramLoop.dout)
def configEp(ep):
ep._updateParamsFrom(self)
rltSig10 = self._sig("sig", Bits(self.DATA_WIDTH), def_val=10)
interfaceMap = IntfMap([
(rltSig10, "rltSig10"),
(self.signalLoop.dout, "signal"),
(self.regCntrlLoop.din, "regCntrl"),
(self.vldSyncedLoop.din, "vldSynced"),
(self.bramLoop.din, "bram"),
(Bits(self.DATA_WIDTH), None),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
axiLiteConv.decoded.vldSynced.din(None)
propagateClkRstn(self)
def mySetUp(self, data_width=32):
u = AxiLiteEndpoint(self.STRUCT_TEMPLATE,
shouldEnterFn=lambda x: (True, isinstance(x.dtype, Bits)))
self.u = u
self.DATA_WIDTH = data_width
u.DATA_WIDTH.set(self.DATA_WIDTH)
self.prepareUnit(self.u, onAfterToRtl=self.mkRegisterMap)
return u
def mySetUp(self, data_width=32, STRUCT_TEMPLATE=None):
if STRUCT_TEMPLATE is None:
STRUCT_TEMPLATE = self.STRUCT_TEMPLATE
u = self.u = AxiLiteEndpoint(STRUCT_TEMPLATE)
self.DATA_WIDTH = data_width
u.DATA_WIDTH.set(self.DATA_WIDTH)
self.prepareUnit(self.u, onAfterToRtl=self.mkRegisterMap)
return u
class SimpleAxiRegs(Unit):
"""
Axi litle mapped registers example,
0x0 - reg0
0x4 - reg1
.. hwt-autodoc::
"""
def _config(self):
self.ADDR_WIDTH = Param(8)
self.DATA_WIDTH = Param(32)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axi = Axi4Lite()
with self._paramsShared():
# this structure is configuration of interfaces
# fields can also be arrays and metaclass can be used
# to specify field interface and R/W access to field
self.conv = AxiLiteEndpoint(
HStruct((uint32_t, "reg0"),
(uint32_t, "reg1")
))
def _impl(self):
propagateClkRstn(self)
self.conv.bus(self.axi, fit=True)
reg0 = self._reg("reg0", Bits(32), def_val=0)
reg1 = self._reg("reg1", Bits(32), def_val=1)
conv = self.conv
def connectRegToConveror(convPort, reg):
If(convPort.dout.vld,
reg(convPort.dout.data)
)
convPort.din(reg)
connectRegToConveror(conv.decoded.reg0, reg0)
connectRegToConveror(conv.decoded.reg1, reg1)
def mySetUp(self, data_width=32, STRUCT_TEMPLATE=None):
if STRUCT_TEMPLATE is None:
STRUCT_TEMPLATE = self.STRUCT_TEMPLATE
u = self.u = AxiLiteEndpoint(STRUCT_TEMPLATE)
self.DATA_WIDTH = data_width
u.DATA_WIDTH = self.DATA_WIDTH
self.compileSimAndStart(self.u, onAfterToRtl=self.mkRegisterMap)
return u
def _impl(self) -> None:
ram = self.ram
al = AxiBuilder(self, self.s).to_axi(Axi4Lite).end
with self._paramsShared():
dec = self.decoder = AxiLiteEndpoint(
HStruct((ram.port[0].dout._dtype[2**ram.ADDR_WIDTH], "ram")))
dec.bus(al)
ram.port[0](dec.decoded.ram)
propagateClkRstn(self)
def _add_ep(self):
strb_w = self.DATA_WIDTH // 8
# [TODO] hotfix, should be self.DATA_WIDTH
DATA_FIELD_W = self.CNTRL_DATA_WIDTH
LEN_WIDTH = self.m_axi.LEN_WIDTH
LOCK_WIDTH = self.m_axi.LOCK_WIDTH
mem_space = HStruct(
(Bits(32), "id_reg"), # 0x00
(Bits(32), "cmd_and_status"),
(Bits(self.ADDR_WIDTH), "addr"),
# a or w id
(Bits(self.ID_WIDTH), "ar_aw_w_id"),
(Bits(32 - int(self.ID_WIDTH)), None),
(Bits(2), "burst"), # 0x10
(Bits(32 - 2), None),
(Bits(4), "cache"),
(Bits(32 - 4), None),
(Bits(LEN_WIDTH), "len"),
(Bits(32 - LEN_WIDTH), None),
(Bits(LOCK_WIDTH), "lock"),
(Bits(32 - LOCK_WIDTH), None),
(Bits(3), "prot"), # 0x20
(Bits(32 - 3), None),
(Bits(3), "size"),
(Bits(32 - 3), None),
(Bits(4), "qos"),
(Bits(32 - 4), None),
(Bits(self.ID_WIDTH), "r_id"),
(Bits(32 - int(self.ID_WIDTH)), None),
(Bits(DATA_FIELD_W), "r_data"), # 0x30
(Bits(2), "r_resp"),
(Bits(32 - 2), None),
(BIT, "r_last"),
(Bits(32 - 1), None),
(Bits(self.ID_WIDTH), "b_id"),
(Bits(32 - int(self.ID_WIDTH)), None),
(Bits(2), "b_resp"), # 0x40
(Bits(32 - 2), None),
(Bits(DATA_FIELD_W), "w_data"),
(BIT, "w_last"),
(Bits(32 - 1), None),
(Bits(strb_w), "w_strb"),
(Bits(32 - int(strb_w)), None),
# 0x50
(Bits(5 * 2), "hs"),
(Bits(5 * 2 - 1), None),
)
ep = self.axi_ep = AxiLiteEndpoint(mem_space, intfCls=self._cntrlCls)
ep.DATA_WIDTH.set(self.CNTRL_DATA_WIDTH)
ep.ADDR_WIDTH.set(self.CNTRL_ADDR_WIDTH)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl._replaceParam(cntrl.ADDR_WIDTH, self.CNTRL_AW)
cntrl._replaceParam(cntrl.DATA_WIDTH, self.DATA_WIDTH)
regs.ADDR_WIDTH.set(self.CNTRL_AW)
regs.DATA_WIDTH.set(self.DATA_WIDTH)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.axi.HAS_R = False
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl.ADDR_WIDTH = self.CNTRL_AW
cntrl.DATA_WIDTH = self.DATA_WIDTH
regs.ADDR_WIDTH = self.CNTRL_AW
regs.DATA_WIDTH = self.DATA_WIDTH
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axis_out = AxiStream()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = Axi4Lite()
reg_t = Bits(self.CNTRL_DATA_WIDTH)
self.conv = AxiLiteEndpoint(
HStruct((reg_t, "enable"),
(reg_t, "len")
)
)
def _declr(self):
assert self.CNTRL_ADDR_WIDTH >= self.CNTR_WIDTH
addClkRstn(self)
with self._paramsShared():
self.master = self._axiCls()._m()
self.slave = self._axiCls()
self.cntrl = Axi4Lite()
mem_space = HStruct((Bits(1), "control"), (Bits(32 - 1), None),
(Bits(32), "ar"), (Bits(32), "aw"),
(Bits(32), "r"), (Bits(32), "w"), (Bits(32), "b"))
ep = self.axi_ep = AxiLiteEndpoint(mem_space)
ep.ADDR_WIDTH.set(self.CNTRL_ADDR_WIDTH)
ep.DATA_WIDTH.set(self.CNTRL_DATA_WIDTH)
self.cntrl.ADDR_WIDTH.set(self.CNTRL_ADDR_WIDTH)
self.cntrl.DATA_WIDTH.set(self.CNTRL_DATA_WIDTH)
def test_itIsPossibleToSerializeIpcores(self):
f = Fifo()
f.DEPTH.set(16)
en0 = AxiS_en()
en0.USE_STRB.set(True)
en0.USE_KEEP.set(True)
en0.ID_WIDTH.set(8)
en0.DEST_WIDTH.set(4)
en0.USER_WIDTH.set(12)
testUnits = [
AxiS_en(), en0,
AxiLiteEndpoint(HStruct((uint64_t, "f0"), (uint64_t[10], "arr0"))),
I2cMasterBitCtrl(), f,
Axi4streamToMem(),
IpCoreIntfTest()
]
for u in testUnits:
serializeAsIpcore(u, folderName=self.test_dir)
def _impl(self):
self.regCntrlOut0(self.regCntrlLoop0.dout)
self.regCntrlOut1(self.regCntrlLoop1.dout)
self.regCntrlOut2(self.regCntrlLoop2.dout)
def configEp(ep):
ep._updateParamsFrom(self)
interfaceMap = IntfMap([
([self.regCntrlLoop0.din,
self.regCntrlLoop1.din,
self.regCntrlLoop2.din,
], "regCntrl"),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
propagateClkRstn(self)
def _impl(self):
self.regCntrlOut0(self.regCntrlLoop0.dout)
self.regCntrlOut1(self.regCntrlLoop1.dout)
self.regCntrlOut2(self.regCntrlLoop2.dout)
def configEp(ep):
ep._updateParamsFrom(self)
interfaceMap = IntfMap([
([self.regCntrlLoop0.din,
self.regCntrlLoop1.din,
self.regCntrlLoop2.din,
], "regCntrl"),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
propagateClkRstn(self)
class AxisFrameGen(Unit):
"""
Generator of axi stream frames for testing purposes
.. hwt-schematic::
"""
def _config(self):
self.MAX_LEN = Param(511)
self.CNTRL_ADDR_WIDTH = Param(4)
self.CNTRL_DATA_WIDTH = Param(32)
self.DATA_WIDTH = Param(64)
self.USE_STRB = Param(True)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axis_out = AxiStream()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = Axi4Lite()
reg_t = Bits(self.CNTRL_DATA_WIDTH)
self.conv = AxiLiteEndpoint(
HStruct((reg_t, "enable"),
(reg_t, "len")
)
)
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld,
connect(cEn.dout.data, en, fit=True)
)
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld,
connect(cLen.dout.data, _len, fit=True)
)
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld,
connect(cLen.dout.data, cntr, fit=True)
).Else(
If(out.ready & en,
If(cntr._eq(0),
cntr(_len)
).Else(
cntr(cntr - 1)
)
)
)
def _declr(self):
BusEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
self.reg = AxiLiteReg(self._intfCls)
def _declr(self):
AxiLiteEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)
self.remap = AxiStaticRemap(Axi4Lite)
def _declr(self):
BusEndpoint._declr(self)
with self._paramsShared():
self.ep = AxiLiteEndpoint(self.STRUCT_TEMPLATE)