def test_3x128(self, N=128): u = self.u m = AxiSimRam(axiAW=u.aw, axiW=u.w, axiB=u.b) _mask = mask(self.DATA_WIDTH // 8) data = [[self._rand.getrandbits(self.DATA_WIDTH) for _ in range(N)] for _ in range(self.DRIVER_CNT)] dataAddress = [ m.malloc(N * self.DATA_WIDTH // 8) for _ in range(self.DRIVER_CNT) ] for di, _data in enumerate(data): req = u.drivers[di].req._ag wIn = u.drivers[di].w._ag dataIt = iter(_data) addr = dataAddress[di] end = False while True: frameSize = self._rand.getrandbits(4) + 1 frame = [] try: for _ in range(frameSize): frame.append(next(dataIt)) except StopIteration: end = True if frame: req.data.append( Axi_datapumpTC.mkReq(self, addr, len(frame) - 1)) wIn.data.extend([(d, _mask, i == len(frame) - 1) for i, d in enumerate(frame)]) addr += len(frame) * self.DATA_WIDTH // 8 if end: break r = self.randomize for d in u.drivers: r(d.req) r(d.w) r(d.ack) r(u.aw) r(u.w) r(u.b) self.runSim(self.DRIVER_CNT * N * 40 * Time.ns) for i, baseAddr in enumerate(dataAddress): inMem = m.getArray(baseAddr, self.DATA_WIDTH // 8, N) self.assertValSequenceEqual(inMem, data[i], f"driver:{i:d}")
def test_1024random(self): u = self.u req = u.driver._ag.req wIn = u.driver.w._ag dataMask = mask(u.DATA_WIDTH // 8) m = AxiSimRam(axi=u.axi) N = 1024 data = [self._rand.getrandbits(u.DATA_WIDTH) for _ in range(N)] buff = m.malloc(N * (u.DATA_WIDTH // 8)) dataIt = iter(data) end = False addr = 0 while True: frameSize = self._rand.getrandbits( self.LEN_MAX_VAL.bit_length()) + 1 frame = [] try: for _ in range(frameSize): frame.append(next(dataIt)) except StopIteration: end = True if frame: req.data.append(self.mkReq(addr, len(frame) - 1)) wIn.data.extend([(d, dataMask, i == len(frame) - 1) for i, d in enumerate(frame)]) addr += len(frame) * u.DATA_WIDTH // 8 if end: break ra = self.randomize ra(u.axi.aw) ra(u.axi.b) ra(u.driver.req) ra(u.driver.ack) ra(u.axi.w) ra(u.driver.w) self.runSim(N * 5 * CLK_PERIOD) inMem = m.getArray(buff, u.DATA_WIDTH // 8, N) self.assertValSequenceEqual(inMem, data)
def test_simpleTransfer(self): u = self.u regs = self.regs N = 33 sampleData = [ self._rand.getrandbits(self.DATA_WIDTH) for _ in range(N) ] m = AxiSimRam(u.axi) blockPtr = m.malloc(self.DATA_WIDTH // 8 * N) u.dataIn._ag.data.extend(sampleData) regs.baseAddr.write(blockPtr) regs.control.write(1) self.runSim(N * 3 * CLK_PERIOD) self.assertValSequenceEqual( m.getArray(blockPtr, self.DATA_WIDTH // 8, N), sampleData)