def write_bit012(pe, bit0: Bit, bit1: Bit, bit2: Bit, instr=asm.add()):
BV1 = BitVector[1]
config_addr = Data8(BIT012_ADDR)
config_data = BitVector.concat(
BitVector.concat(BitVector.concat(BV1(bit0), BV1(bit1)), BV1(bit2)),
BitVector[29](0))
config_en = Bit(1)
return pe(instr,
data0=Data(0),
config_addr=config_addr,
config_data=config_data,
config_en=config_en)
def write_data01(pe, data0: Data, data1: Data, instr=asm.add(), ra=Data(0)):
config_addr = Data8(DATA01_ADDR)
config_data = BitVector.concat(data0, data1)
config_en = Bit(1)
return pe(instr,
data0=ra,
config_addr=config_addr,
config_data=config_data,
config_en=config_en)
def tile_id_physical(interconnect: Interconnect):
tile_id_width = interconnect.tile_id_width
tie_hi_width = (tile_id_width // 2) + 1
if (tile_id_width % 2) == 0:
tie_lo_width = tile_id_width // 2
else:
tie_lo_width = (tile_id_width // 2) + 1
for (x, y) in interconnect.tile_circuits:
tile = interconnect.tile_circuits[(x, y)]
tile_core = tile.core
if isinstance(tile_core, IOCoreValid) or tile_core is None:
continue
tile.add_ports(hi=magma.Out(magma.Bits[tie_hi_width]),
lo=magma.Out(magma.Bits[tie_lo_width]))
# wire all hi bits high
tile.wire(tile.ports.hi, Const((2**tie_hi_width) - 1))
# wire all lo bits low
tile.wire(tile.ports.lo, Const(0))
# Get the correct tile_id value
x_bv = BitVector[tile_id_width / 2](x)
y_bv = BitVector[tile_id_width / 2](y)
tile_id_bv = BitVector.concat(y_bv, x_bv)
# Disconnect existing constant from tile_id port
tile_id_port = tile.ports.tile_id
for wire in interconnect.wires:
if tile_id_port in wire:
interconnect.remove_wire(wire[0], wire[1])
break
# Actually connect hi/lo outputs to tile_id at top level
for i in range(tile_id_width):
lo_index = i // 2
if (i % 2) == 0:
hi_index = i // 2
else:
hi_index = (i // 2) + 1
hi_port = tile.ports.hi[hi_index]
lo_port = tile.ports.lo[lo_index]
tie_port = hi_port if (tile_id_bv[i] == 1) else lo_port
# Connect tile_id ports to hi/lo outputs instead of constant
interconnect.wire(tile.ports.tile_id[i], tie_port)
def BFloat(fpdata):
sign = BitVector[1](fpdata.sign)
exp = BitVector[8](fpdata.exp)
frac = BitVector[7](fpdata.frac)
return BitVector.concat(BitVector.concat(frac, exp), sign)