def __init__(self, tile, lcidx):
self.lut = ''.join(icebox.get_lutff_lut_bits(tile.data, lcidx))
self.expr = lut_to_logic_expression(
self.lut, ('in_0', 'in_1', 'in_2', 'in_3'))
self.options = []
lutff_option_bits = ''.join(icebox.get_lutff_seq_bits(tile.data, lcidx))
if lutff_option_bits[0] == '1': self.options.append('enable_carry')
if lutff_option_bits[1] == '1': self.options.append('enable_dff')
if lutff_option_bits[2] == '1': self.options.append('set_noreset')
if lutff_option_bits[3] == '1': self.options.append('async_setreset')
self.buffer_and_routing0 = set()
self.buffer_and_routing1 = set()
for br in tuple(tile.buffer_and_routing):
if br[0] == 'lutff_%d/out' % lcidx:
self.buffer_and_routing1.add((br[0][8:], ) + br[1:])
tile.used_buffer_and_routing.add(br)
elif br[-1].startswith('lutff_%d/' % lcidx):
self.buffer_and_routing0.add(br[:-1] + (br[-1][8:], ))
tile.used_buffer_and_routing.add(br)
def __init__(self, tile, lcidx):
self.lut = ''.join(icebox.get_lutff_lut_bits(tile.data, lcidx))
self.expr = lut_to_logic_expression(self.lut,
('in_0', 'in_1', 'in_2', 'in_3'))
self.options = []
lutff_option_bits = ''.join(icebox.get_lutff_seq_bits(
tile.data, lcidx))
if lutff_option_bits[0] == '1': self.options.append('enable_carry')
if lutff_option_bits[1] == '1': self.options.append('enable_dff')
if lutff_option_bits[2] == '1': self.options.append('set_noreset')
if lutff_option_bits[3] == '1': self.options.append('async_setreset')
self.buffer_and_routing0 = set()
self.buffer_and_routing1 = set()
for br in tuple(tile.buffer_and_routing):
if br[0] == 'lutff_%d/out' % lcidx:
self.buffer_and_routing1.add((br[0][8:], ) + br[1:])
tile.used_buffer_and_routing.add(br)
elif br[-1].startswith('lutff_%d/' % lcidx):
self.buffer_and_routing0.add(br[:-1] + (br[-1][8:], ))
tile.used_buffer_and_routing.add(br)
text_func.append(" .WCLK%s(%s)," % ("N" if negclk_wr else "", get_ram_wire('WCLK', 0, 0)))
text_func.append(" .RE(%s)," % get_ram_wire('RE', 0, 0))
text_func.append(" .RCLKE(%s)," % get_ram_wire('RCLKE', 0, 0, "1'b1"))
text_func.append(" .RCLK%s(%s)" % ("N" if negclk_rd else "", get_ram_wire('RCLK', 0, 0)))
text_func.append(");")
text_func.append("")
wire_to_reg = set()
lut_assigns = list()
const_assigns = list()
carry_assigns = list()
always_stmts = list()
max_net_len = 0
for lut in luts_queue:
seq_bits = icebox.get_lutff_seq_bits(ic.logic_tiles[(lut[0], lut[1])], lut[2])
if seq_bits[0] == "1":
seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2]))
for lut in luts_queue:
tile = ic.logic_tiles[(lut[0], lut[1])]
lut_bits = icebox.get_lutff_lut_bits(tile, lut[2])
seq_bits = icebox.get_lutff_seq_bits(tile, lut[2])
net_in0 = seg_to_net((lut[0], lut[1], "lutff_%d/in_0" % lut[2]), "1'b0")
net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "1'b0")
net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "1'b0")
net_in3 = seg_to_net((lut[0], lut[1], "lutff_%d/in_3" % lut[2]), "1'b0")
net_out = seg_to_net((lut[0], lut[1], "lutff_%d/out" % lut[2]))
net_lout = seg_to_net((lut[0], lut[1], "lutff_%d/lout" % lut[2]))
if seq_bits[0] == "1":
net_cout = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2]))
if ic.tile_type(seg[0],
seg[1]) == "LOGIC" and seg[2].startswith("lutff_"):
match = re.match("lutff_(\d)/in_\d", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
lut_locations.add(loc)
match = re.match("lutff_(\d)/cout", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
carry_locations.add(loc)
match = re.match("lutff_(\d)/out", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
seq_bits = icebox.get_lutff_seq_bits(ic.tile(loc[0], loc[1]),
loc[2])
if seq_bits[1] == "1":
dff_locations.add(loc)
if ic.tile_type(
seg[0],
seg[1]) in ("RAMB", "RAMT") and seg[2].startswith("ram/"):
loc = (seg[0], seg[1] - (seg[1] % 2))
bram_locations.add(loc)
if seg[2].startswith("glb_netwk_"):
match = re.match("glb_netwk_(\d)", seg[2])
if match:
global_nets.add(int(match.group(1)))
pll_config_bitidx = dict()
def print_tile(stmt, ic, x, y, tile, db):
if single_tile is not None and single_tile != (x, y):
return
bits = set()
mapped_bits = set()
for k, line in enumerate(tile):
for i in range(len(line)):
if line[i] == "1":
bits.add("B%d[%d]" % (k, i))
else:
bits.add("!B%d[%d]" % (k, i))
if re.search(r"logic_tile", stmt):
active_luts = set([i for i in range(8) if "1" in icebox.get_lutff_bits(tile, i)])
text = set()
used_lc = set()
text_default_mask = 0
for entry in db:
if re.match(r"LC_", entry[1]):
continue
if entry[1] in ("routing", "buffer"):
if not ic.tile_has_net(x, y, entry[2]):
continue
if not ic.tile_has_net(x, y, entry[3]):
continue
match = True
for bit in entry[0]:
if not bit in bits:
match = False
if match:
for bit in entry[0]:
mapped_bits.add(bit)
if entry[1] == "IoCtrl" and entry[2] == "IE_0":
text_default_mask |= 1
if entry[1] == "IoCtrl" and entry[2] == "IE_1":
text_default_mask |= 2
if entry[1] == "RamConfig" and entry[2] == "PowerUp":
text_default_mask |= 4
if print_bits:
text.add("<%s> %s" % (" ".join(entry[0]), " ".join(entry[1:])))
else:
text.add(" ".join(entry[1:]))
bitinfo = list()
print_bitinfo = False
for k, line in enumerate(tile):
bitinfo.append("")
extra_text = ""
for i in range(len(line)):
if 36 <= i <= 45 and re.search(r"logic_tile", stmt):
lutff_idx = k // 2
lutff_bitnum = (i - 36) + 10 * (k % 2)
if line[i] == "1":
used_lc.add(lutff_idx)
bitinfo[-1] += "*"
else:
bitinfo[-1] += "-"
elif line[i] == "1" and "B%d[%d]" % (k, i) not in mapped_bits:
print_bitinfo = True
extra_text += " B%d[%d]" % (k, i)
bitinfo[-1] += "?"
else:
bitinfo[-1] += "+" if line[i] == "1" else "-"
bitinfo[-1] += extra_text
for lcidx in sorted(used_lc):
lutff_options = "".join(icebox.get_lutff_seq_bits(tile, lcidx))
if lutff_options[0] == "1":
lutff_options += " CarryEnable"
if lutff_options[1] == "1":
lutff_options += " DffEnable"
if lutff_options[2] == "1":
lutff_options += " Set_NoReset"
if lutff_options[3] == "1":
lutff_options += " AsyncSetReset"
text.add("LC_%d %s %s" % (lcidx, "".join(icebox.get_lutff_lut_bits(tile, lcidx)), lutff_options))
if not print_bitinfo and not print_all:
if text_default_mask == 3 and len(text) == 2:
return
if text_default_mask == 4 and len(text) == 1:
return
if len(text) or print_bitinfo or print_all:
print("\n%s" % stmt)
if print_bitinfo:
print("Warning: No DB entries for some bits:")
if print_bitinfo or print_map:
for k, line in enumerate(bitinfo):
print("%4s %s" % ("B%d" % k, line))
for line in sorted(text):
print(line)
def print_tile(stmt, ic, x, y, tile, db):
if single_tile is not None and single_tile != (x, y):
return
bits = set()
mapped_bits = set()
for k, line in enumerate(tile):
for i in range(len(line)):
if line[i] == "1":
bits.add("B%d[%d]" % (k, i))
else:
bits.add("!B%d[%d]" % (k, i))
if re_search_cached(r"logic_tile", stmt):
active_luts = set([i for i in range(8) if "1" in icebox.get_lutff_bits(tile, i)])
text = set()
used_lc = set()
text_default_mask = 0
for entry in db:
if re_match_cached(r"LC_", entry[1]):
continue
if entry[1] in ("routing", "buffer"):
if not ic.tile_has_net(x, y, entry[2]): continue
if not ic.tile_has_net(x, y, entry[3]): continue
match = True
for bit in entry[0]:
if not bit in bits:
match = False
if match:
for bit in entry[0]:
mapped_bits.add(bit)
if entry[1] == "IoCtrl" and entry[2] == "IE_0":
text_default_mask |= 1
if entry[1] == "IoCtrl" and entry[2] == "IE_1":
text_default_mask |= 2
if entry[1] == "RamConfig" and entry[2] == "PowerUp":
text_default_mask |= 4
if print_bits:
text.add("<%s> %s" % (" ".join(entry[0]), " ".join(entry[1:])))
else:
text.add(" ".join(entry[1:]))
bitinfo = list()
print_bitinfo = False
for k, line in enumerate(tile):
bitinfo.append("")
extra_text = ""
for i in range(len(line)):
if 36 <= i <= 45 and re_search_cached(r"(logic_tile|dsp\d_tile|ipcon_tile)", stmt):
lutff_idx = k // 2
lutff_bitnum = (i-36) + 10*(k%2)
if line[i] == "1":
used_lc.add(lutff_idx)
bitinfo[-1] += "*"
else:
bitinfo[-1] += "-"
elif line[i] == "1" and "B%d[%d]" % (k, i) not in mapped_bits:
print_bitinfo = True
extra_text += " B%d[%d]" % (k, i)
bitinfo[-1] += "?"
else:
bitinfo[-1] += "+" if line[i] == "1" else "-"
bitinfo[-1] += extra_text
for lcidx in sorted(used_lc):
lutff_options = "".join(icebox.get_lutff_seq_bits(tile, lcidx))
if lutff_options[0] == "1": lutff_options += " CarryEnable"
if lutff_options[1] == "1": lutff_options += " DffEnable"
if lutff_options[2] == "1": lutff_options += " Set_NoReset"
if lutff_options[3] == "1": lutff_options += " AsyncSetReset"
text.add("LC_%d %s %s" % (lcidx, "".join(icebox.get_lutff_lut_bits(tile, lcidx)), lutff_options))
if not print_bitinfo and not print_all:
if text_default_mask == 3 and len(text) == 2:
return
if text_default_mask == 4 and len(text) == 1:
return
if len(text) or print_bitinfo or print_all:
print("\n%s" % stmt)
if print_bitinfo:
print("Warning: No DB entries for some bits:")
if print_bitinfo or print_map:
for k, line in enumerate(bitinfo):
print("%4s %s" % ("B%d" % k, line))
for line in sorted(text):
print(line)
if ic.tile_type(seg[0], seg[1]) == "LOGIC" and seg[2].startswith("lutff_"):
match = re.match("lutff_(\d)/in_\d", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
lut_locations.add(loc)
match = re.match("lutff_(\d)/cout", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
carry_locations.add(loc)
match = re.match("lutff_(\d)/out", seg[2])
if match:
loc = (seg[0], seg[1], int(match.group(1)))
seq_bits = icebox.get_lutff_seq_bits(ic.tile(loc[0], loc[1]), loc[2])
if seq_bits[1] == "1":
dff_locations.add(loc)
if ic.tile_type(seg[0], seg[1]) in ("RAMB", "RAMT") and seg[2].startswith("ram/"):
loc = (seg[0], seg[1] - (seg[1] % 2))
bram_locations.add(loc)
if seg[2].startswith("glb_netwk_"):
match = re.match("glb_netwk_(\d)", seg[2])
if match:
global_nets.add(int(match.group(1)))
pll_config_bitidx = dict()
for entry in icebox.iotile_l_db:
