def test4():
I1 = ila.Abstraction('a')
inp1 = I1.inp('inp', 1)
r1 = I1.reg('r1', 5)
r1a = I1.reg('ra', 5)
I1.decode_exprs = [inp1 == 1, inp1 == 0]
uI1 = I1.add_microabstraction("mic", (r1 != 0))
I1.set_next('r1', ila.ite(inp1 == 1, I1.const(1, 5), I1.const(0, 5)))
I1.set_next('ra', r1a)
ur1 = uI1.reg('ur1', 5)
r1p = uI1.getreg('r1')
uI1.set_init('ur1', uI1.const(0, 5))
uI1.set_next('ur1', ur1 + 1)
ura1 = uI1.getreg('ra')
uI1.set_next('ra', ura1 - 1)
uI1.set_next('r1', ila.ite(ura1 == 1, I1.const(0, 5), I1.const(1, 5)))
#######################
I2 = ila.Abstraction('b')
inp2 = I2.inp('inp', 1)
r2 = I2.reg('r1', 5)
r2a = I2.reg('ra', 5)
I2.decode_exprs = [inp2 == 1, inp2 == 0]
uI2 = I2.add_microabstraction("mic", (r2 != 0))
I2.set_next('r1', ila.ite(inp2 == 1, I2.const(1, 5), I2.const(0, 5)))
I2.set_next('ra', r2a)
ur2 = uI2.reg('ur1', 5)
r2p = uI2.getreg('r1')
uI2.set_init('ur1', uI2.const(0, 5))
uI2.set_next('ur1', ur2 + 1)
ura2 = uI2.getreg('ra')
uI2.set_next('ra', uI2.getreg('ra') - 1)
uI2.set_next('r1', ila.ite(ura2 == 1, I2.const(0, 5), I2.const(1, 5)))
print 'simple signature test:'
print ila.eqcheckSimple(I1, I2)
print 'full test'
u1 = I1.newUnroller(uI1, False)
u1.unrollTo(4)
u2 = I2.newUnroller(uI2, False)
u2.unrollTo(4)
inductiveAssumpt = [(1, "r1", "r1"), (1, "ra", "ra"), (1, "ur1", "ur1")]
print ila.eqcheck(u1, u2, "r1", "r1", inductiveAssumpt)
print ila.eqcheck(u1, u2, "ra", "ra", inductiveAssumpt)
print ila.eqcheck(u1, u2, "ur1", "ur1", inductiveAssumpt)
def main():
iteAsNode = False
iteAsNode = True
hornFile = "tmp/horn_test_node.smt2"
A = getDummyILA()
ila.setloglevel(3, "")
ila.enablelog("Horn")
A.hornifyAll("tmp/horn_test_ILA.smt2")
r2_nxt = A.get_next('r2')
A.hornifyNode(r2_nxt, "r2_nxt")
A.exportHornToFile(hornFile)
m = ila.Abstraction("fun")
x = m.reg('x', 8)
y = m.reg('y', 16)
f = m.fun('foo', 8, [8, 16])
r = ila.appfun(f, x, y)
m.hornifyBvAsInt(True)
m.hornifyNode(r, "foo")
m.exportHornToFile(hornFile)
alu = ila.Abstraction("alu")
alu.hornifyBvAsInt(True)
aluFile = 'tmp/alu.txt'
if not os.path.exists(aluFile):
print 'alu file not exist'
return
alu.importAll(aluFile)
r0_nxt = alu.get_next('r0')
r1_nxt = alu.get_next('r1')
pc_nxt = alu.get_next('pc')
rom_nxt = alu.get_next('rom')
"""
alu.hornifyNode(pc_nxt, "pc_nxt")
alu.hornifyNode(r0_nxt, "r0_nxt")
alu.hornifyNode(r1_nxt, "r1_nxt")
alu.hornifyNode(rom_nxt, "rom_nxt")
alu.exportHornToFile(hornFile)
"""
alu.addHornInstr('alu_instr', alu.bool(True))
alu.addHornNext('alu_instr', 'pc', pc_nxt)
alu.addHornNext('alu_instr', 'r0', r0_nxt)
alu.addHornNext('alu_instr', 'r1', r1_nxt)
alu.addHornNext('alu_instr', 'rom', rom_nxt)
alu.addHornChild('alu_child', 'alu_instr', alu.bool(True))
alu.addHornNext('alu_child', 'pc', pc_nxt)
alu.addHornNext('alu_child', 'r0', r0_nxt)
alu.addHornNext('alu_child', 'r1', r1_nxt)
alu.addHornNext('alu_child', 'rom', rom_nxt)
alu.generateHornMapping('Interleave')
#alu.generateHornMapping ('Blocking')
alu.exportHornToFile(hornFile)
def loadILAs(vname, cname):
vILA = ila.Abstraction('vaes')
vILA.importAll(os.path.join(vname, 'all'))
vuILA = vILA.get_microabstraction('aes_compute')
vuILA.importAll(os.path.join(vname, 'allu'))
cILA = ila.Abstraction('caes')
cILA.importAll(os.path.join(cname, 'all'))
cuILA = cILA.get_microabstraction('aes_compute')
cuILA.importAll(os.path.join(cname, 'allu'))
return (vILA, vuILA, cILA, cuILA)
def loadILAs():
vILA = ila.Abstraction('vaes')
vILA.importAll('vILA/all')
vuILA = vILA.get_microabstraction('aes_compute')
vuILA.importAll('vILA/allu')
cILA = ila.Abstraction('caes')
cILA.importAll('cILA/all')
cuILA = cILA.get_microabstraction('aes_compute')
cuILA.importAll('cILA/allu')
return (vILA, vuILA, cILA, cuILA)
def test3():
I1 = ila.Abstraction('a')
inp1 = I1.inp('inp', 1)
r1 = I1.reg('r1', 5)
I1.decode_exprs = [inp1 == 1, inp1 == 0]
uI1 = I1.add_microabstraction("mic", (r1 != 0) & (r1 < 2))
I1.set_next('r1', ila.ite(inp1 == 1, I1.const(1, 5), I1.const(0, 5)))
ur1 = uI1.reg('ur1', 5)
r1p = uI1.getreg('r1')
uI1.set_init('ur1', uI1.const(0, 5))
uI1.set_next('ur1', ur1 + 1)
uI1.set_next('r1', ila.ite(ur1 > 5, ur1, r1p))
#######################
I2 = ila.Abstraction('b')
inp2 = I2.inp('inp', 1)
r2 = I2.reg('r1', 5)
uI2 = I2.add_microabstraction("mic", (r2 != 0) & (r2 < 2))
I2.set_next('r1', ila.ite(inp2 == 1, I2.const(1, 5), I2.const(0, 5)))
I2.decode_exprs = [inp2 == 1, inp2 == 0]
ur2 = uI2.reg('ur1', 5)
r2p = uI2.getreg('r1')
uI2.set_init('ur1', uI1.const(0, 5))
uI2.set_next('ur1', ur2 + 3)
uI2.set_next('r1', ila.ite(ur2 > 5, ur2, r2p))
print 'simple signature test:'
print ila.eqcheckSimple(I1, I2)
print 'full test'
u1 = I1.newUnroller(uI1, True)
u1.addAssumption(inp1 == 1)
u1.unrollTo(20)
u1.checkAssertion(~(uI1.fetch_valid))
u1.checkAssertion(r1 == 6)
u2 = I2.newUnroller(uI2, True)
u2.addAssumption(inp2 == 1)
u2.unrollTo(20)
u2.checkAssertion(~(uI2.fetch_valid))
u2.checkAssertion(r2 == 6)
print ila.eqcheck(u1, u2, 'r1', 'r1')
def __init__(self):
self.model = ila.Abstraction('GPU_ptx')
self.bar_spec = barSpec()
self.thread_num = 2
self.createStates()
self.set_init()
self.add_assumptions()
def createHorn():
all_addrs = [addr for addr in xrange(0xfe00, 0xfe04)]
all_child = [1, 2, 3, 4]
all_states = ['acc_state', 'bytes_read']
m = ila.Abstraction('acc')
chcPath = '../horn'
if not os.path.exists(chcPath):
os.makedirs(chcPath)
for addr in all_addrs:
decodePath = 'asts/0x%x/decode' % addr
decode = m.importOne(decodePath)
m.hornifyNode(decode, 'decode_%x' % addr, True)
for s in all_states:
nxtPath = 'asts/0x%x/%s' % (addr, s)
nxt = m.importOne(nxtPath)
m.hornifyNode(nxt, 'instr_%x_%s_nxt' % (addr, s), True)
for st in all_child:
decodePath = 'asts/st%d/decode' % st
decode = m.importOne(decodePath)
m.hornifyNode(decode, 'decode_st%d' % st, True)
for s in all_states:
nxtPath = 'asts/st%d/%s' % (st, s)
nxt = m.importOne(nxtPath)
m.hornifyNode(nxt, 'child_%d_%s_nxt' % (st, s), True)
m.exportHornToFile('%s/ila.smt' % chcPath)
def set_init(self):
bar_spec = ptxILA.barSpec()
self.a_is_bar = (self.opcode_a == bar_spec.BAR_OPCODE)
#self.a_is_bar = (self.pc_a == 20)
self.a_previous_bar = self.model.bit('a_previous_bar')
self.model.set_next('a_previous_bar', self.a_is_bar)
self.a_cross_bar_flag = self.model.bit('a_cross_bar_flag')
self.model.set_next(
'a_cross_bar_flag',
ila.ite((self.a_is_bar == ila.bool(False)) &
(self.a_previous_bar == ila.bool(True)), ila.bool(True),
self.a_cross_bar_flag))
self.b_is_bar = (self.opcode_b == bar_spec.BAR_OPCODE)
self.b_come_to_bar_flag = self.model.bit('b_come_to_bar_flag')
self.model.set_next(
'b_come_to_bar_flag',
ila.ite(self.b_is_bar, ila.bool(True), self.b_come_to_bar_flag))
self.predicate_one = self.model.bit('predicate_one')
self.model.set_next('predicate_one', (~self.a_cross_bar_flag) |
(self.b_come_to_bar_flag))
self.model.set_init('a_previous_bar', self.model.bool(False))
self.model.set_init('a_cross_bar_flag', self.model.bool(False))
self.model.set_init('b_come_to_bar_flag', self.model.bool(False))
self.model.set_init('predicate_one', self.model.bool(True))
golden = ila.Abstraction('golden')
g_prop = golden.bit('prop')
golden.set_next('prop', golden.bool(True))
golden.set_init('prop', golden.bool(True))
ila.bmc(30, self.model, self.predicate_one, 1, golden, g_prop)
def template():
# Create a model container.
m = ila.Abstraction('tutorial')
# Create/define states in the model.
regs = []
for i in xrange(0, 8):
regName = 'reg{}'.format(i)
regs.append(m.reg(regName, 8))
instr = m.reg('input', 16)
out = m.reg('output', 8)
# Define next state function.
imm = instr[7:0]
src1 = ila.choice('src1', regs + [imm])
src2 = ila.choice('src2', regs + [imm])
out_nxt = ila.choice('out', [src1 + src2, src1 * src2])
# Assign the next state function.
m.set_next('output', out_nxt)
# Define how to decode.
m.decode_exprs = [instr[15:8] == i for i in xrange(0, 0x100)]
return m
def createILA():
m = ila.Abstraction('acc_regs')
# input ports
cmd = m.inp ('cmd', 2)
cmdaddr = m.inp ('cmdaddr', 16)
cmddata = m.inp ('cmddata', 8)
# arch states
state = m.reg ('acc_state', 3)
rd_addr = m.reg ('rd_addr', 16)
wr_addr = m.reg ('wr_addr', 16)
oplen = m.reg ('acc_len', 16)
xram = m.mem ('XRAM', 16, 8)
# micro-arch states
bytes_read = m.reg ('bytes_read', 16)
# fetch function and fetch valid function
m.fetch_expr = ila.concat ([state, cmd, cmdaddr, cmddata])
m.fetch_valid = (cmd == 1) | (cmd == 2)
# state_nxt
state_nxt = ila.choice ('state_nxt', [
m.const (0, 3), m.const (1, 3), m.const (2, 3),
m.const (3, 3), m.const (4, 3), state])
m.set_next ('acc_state', state_nxt)
# NOTE next state functions for rd_addr, wr_addr, oplen and xram is ignore.
return m
def createmodel():
m = ila.Abstraction('alu')
m.enable_parameterized_synthesis = 1
regs = [m.reg('r%d' % i, 8) for i in xrange(4)]
opcode = m.inp('opcode', 7)
rs_index = opcode[1:0]
rt_index = opcode[3:2]
rd_index = opcode[5:4]
op = opcode[6:6]
def sel(regs, idx):
return ila.ite(
idx == 0, regs[0],
ila.ite(idx == 1, regs[1], ila.ite(idx == 2, regs[2], regs[3])))
rs = sel(regs, rs_index)
rt = sel(regs, rt_index)
res = ila.choice('op', rs + rt, rs - rt)
for i in xrange(4):
ri_next = ila.ite(rd_index == i, res, regs[i])
m.set_next('r%d' % i, ri_next)
m.fetch_expr = opcode
m.decode_exprs = [opcode == i for i in xrange(0, 128)]
m.synthesize(alusim)
for i, di in enumerate(m.decode_exprs):
for reg in xrange(4):
exp_i = m.get_next('r%d' % reg, i)
si = ila.simplify(di, exp_i)
if not m.areEqual(di, exp_i, si):
print 'decode:', di
print 'exp:', exp_i
def main():
m = ila.Abstraction('test')
x = m.reg('x', 8)
y = m.reg('y', 8)
ex1 = (x + y) | x
h1 = ex1.__hash__()
ex2 = (x + y) | x
h2 = ex2.__hash__()
x3 = m.getreg('x')
y3 = m.getreg('y')
ex3 = (x3 + y3) | x
h3 = ex3.__hash__()
assert h1 == h2
assert h2 == h3
assert h3 == h1
ex4 = (y + x) | x
h4 = ex4.__hash__()
assert h4 != h1
assert h4 != h2
assert h4 != h3
def __init__(self):
self.model = ila.Abstraction('GPU_ptx')
self.thread_num = 2
self.flag_num = 10
self.current_flag = 0
self.createStates()
self.add_assumptions()
def translate():
all_instrs = [addr for addr in xrange(0xfd00, 0xfe10)]
all_instrs = [0xfd00, 0xfd01]
all_childs = [1, 2, 3]
all_states = [
'rsa_state', 'rsa_addr', 'XRAM', 'rsa_byte_counter', 'rsa_buff',
'rsa_M', 'dataout'
]
m = ila.Abstraction('rsa')
m.hornifyIteAsNode(True)
m.hornifyBvAsInt(True)
dstDir = '../horn'
if not os.path.exists(dstDir):
os.makedirs(dstDir)
root = 'asts'
for addr in all_instrs:
Dpath = root + '/instr_W_%x/decode' % addr
Dast = m.importOne(Dpath)
instrName = 'rsa_w_%x' % addr
#m.hornifyNode (Dast, 'D_%x' % addr)
m.addHornInstr(instrName, Dast)
for s in all_states:
Npath = root + '/instr_W_%x/%s' % (addr, s)
Nast = m.importOne(Npath)
#m.hornifyNode (Nast, 'N_%x_%s' % (addr, s))
m.addHornNext(instrName, s, Nast)
for addr in all_instrs:
Dpath = root + '/instr_R_%x/decode' % addr
Dast = m.importOne(Dpath)
instrName = 'rsa_r_%x' % addr
m.addHornInstr(instrName, Dast)
for s in all_states:
Npath = root + '/instr_R_%x/%s' % (addr, s)
Nast = m.importOne(Npath)
m.addHornNext(instrName, s, Nast)
for st in all_childs:
Dpath = root + '/child_%d/decode' % st
Dast = m.importOne(Dpath)
childName = 'rsa_u_%x' % st
#m.hornifyNode (Dast, 'D_%x' % st)
m.addHornChild(childName, 'rsa_w_fd00', Dast)
for s in all_states:
Npath = root + '/child_%d/%s' % (st, s)
Nast = m.importOne(Npath)
#m.hornifyNode (Nast, 'N_%d_%s' % (st, s))
m.addHornNext(childName, s, Nast)
m.generateHornMapping('Interleave')
ilaFile = dstDir + '/ila.smt2'
m.exportHornToFile(ilaFile)
def main():
expFile = "tmp/test_ila_export.txt"
sys = ila.Abstraction("test")
r0 = sys.reg('r0', 8)
r1 = sys.reg('r1', 8)
a = sys.bit('a')
b = sys.bit('b')
ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1)
resfoo = sys.syn_elem("sum", ex, foo)
assert sys.areEqual(resfoo, r0 + r1)
resbar = sys.syn_elem("diff", ex, bar)
assert sys.areEqual(resbar, r0 - r1)
a1 = ila.choice("a1", a, ~a, a & b, a | b)
b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b])
a2 = ila.choice("a2", a, ~a)
b2 = ila.choice("b2", b, ~b)
t1 = a1 & b1
t2 = a2 & b2
y = t1 | t2
resbaz = sys.syn_elem("baz", y, baz)
assert sys.areEqual(resbaz, a ^ b)
resshaz = sys.syn_elem("shaz", y, shaz)
assert sys.areEqual(resshaz, ~(a ^ b))
c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8))
z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c)
resdaz = sys.syn_elem("daz", z, daz)
assert sys.areEqual(resdaz, r0 + r1 + 0x44)
slc0 = ila.readslice("r0slice", r0, 4)
slc1 = ila.readslice("r1slice", r1, 4)
res = ila.choice('slice', slc0 + slc1, slc0 - slc1)
resrmz = sys.syn_elem("razmatazz", res, razmatazz)
assert sys.areEqual(resrmz, r0[3:0] + r1[7:4])
sys.exportOne(resrmz, expFile)
getback = sys.importOne(expFile)
assert sys.areEqual(resrmz, getback)
print getback
#sys.exportFile(expFile);
#sys.importFile(expFile);
ila.setloglevel(3, "")
ila.enablelog("Export")
sys.exportList([resrmz, resdaz], expFile)
l = sys.importList(expFile)
for ast in l:
print ast
def test():
m1 = ila.Abstraction('t1')
x1 = m1.reg('x', 8)
y1 = m1.reg('y', 8)
m1.set_next('x', x1)
m1.set_init('x', m1.const(1, 8))
m1.set_next('y', y1 + x1)
assert m1.areEqualUnrolled(3, y1, y1 + 3)
assert not m1.areEqualUnrolled(3, y1, y1 + 4)
m2 = ila.Abstraction('t2')
y2 = m2.reg('y', 8)
m2.set_next('y', y2 + 3)
assert m2.areEqualUnrolled(3, y2, y2 + 9)
assert not m2.areEqualUnrolled(3, y2, y2 + 10)
assert ila.bmc(3, m2, y2, 9, m1, y1)
assert not ila.bmc(4, m2, y2, 9, m1, y1)
def getDummyILA():
A = ila.Abstraction("dummy")
r0 = A.reg('r0', 8)
r1 = A.reg('r1', 8)
r2 = A.reg('r2', 8)
r2_nxt = r0 + r1
A.set_next('r2', r2_nxt)
return A
def main():
c = ila.Abstraction("test")
top = c.bool(True)
bot = c.bool(False)
x = c.reg('x', 8)
y = c.reg('y', 8)
g = c.fun('cnst', 8, [])
h1 = ila.appfun(g, [])
h2 = c.const(40, 8)
c.add_assumption((h1 >= 10) & (h1 <= 15))
val = ila.choice('val', h1, h2)
res = val + x + y
def sim(d):
x = d['x']
y = d['y']
d_out = {}
d_out['res'] = (x + y + randint(11, 12)) & 0xff
return d_out
res_s = c.syn_elem('res', res, sim)
assert c.areEqual(res_s, h1 + x + y)
z = c.reg('z', 16)
c0 = c.const(0, 8)
c1 = c.const(1, 8)
cmax = c.const(255, 8)
f = c.fun('foo', 8, [8, 16])
r = ila.appfun(f, x, z)
t = ila.appfun(f, y, z)
eq = x == y
req = r == t
assert c.areEqual(ila.implies(eq, req), top)
assert c.areEqual(r <= cmax, top)
up = c.const(128, 8)
down = c.const(120, 16)
con = ila.implies((x < up) & (z > down), ila.appfun(f, x, z) > up)
test = ila.implies(con & (x == 125) & (z == 125), ila.appfun(f, x, z) > up)
assert c.areEqual(test, top)
x_next = ila.appfun(f, y, z)
c.set_next('x', x_next)
exportFile = 'tmp/test_ila_export.txt'
c.exportAll(exportFile)
c.importAll(exportFile)
simFile = 'tmp/test_ila_sim.hpp'
c.generateSim(simFile)
def genAbst(state, enable_ps):
model = ila.Abstraction("oc8051")
# fetch and decode.
uc = uc8051()
model.fetch_expr = uc.op0 # s/hand for uc.rom[uc.pc]
model.decode_exprs = [uc.op0 == i for i in xrange(0x0, 0x100)]
# program counter
pc = model.reg('PC', 16)
# code memory
rom = model.mem('ROM', 16, 8)
# IRAM
iram = model.mem('IRAM', 8, 8)
# main SFRs
acc = model.reg('ACC', 8)
b = model.reg('B', 8)
psw = model.reg('PSW', 8)
sp = model.reg('SP', 8)
dpl = model.reg('DPL', 8)
dph = model.reg('DPH', 8)
# ports
p0 = model.reg('P0', 8)
p1 = model.reg('P1', 8)
p2 = model.reg('P2', 8)
p3 = model.reg('P3', 8)
# misc SFRs
pcon = model.reg('PCON', 8)
tcon = model.reg('TCON', 8)
tmod = model.reg('TMOD', 8)
tl0 = model.reg('TL0', 8)
tl1 = model.reg('TH0', 8)
tl1 = model.reg('TL1', 8)
th1 = model.reg('TH1', 8)
scon = model.reg('SCON', 8)
sbuf = model.reg('SBUF', 8)
ie = model.reg('IE', 8)
ip = model.reg('IP', 8)
# XRAM
#xram_data_in = model.reg('XRAM_DATA_IN', 8) FIXME
#xram_data_in = model.inp('XRAM_DATA_IN', 8)
xram_data_out = model.reg('XRAM_DATA_OUT', 8)
xram_addr = model.reg('XRAM_ADDR', 16)
# get synthesized states
for s in state:
print 'Import %s from file' % s
ast = model.importOne('asts/%s_%s' % (s, 'en' if enable_ps else 'dis'))
model.set_next(s, ast)
abst_file = 'archive/oc8051.abst'
if not os.path.isdir('archive'):
os.mkdir('archive')
model.exportAll(abst_file)
def bmc():
m = ila.Abstraction('alu')
m.importAll('ALU_moore.ila')
# Create state for property predicate
prop = m.bit('prop')
prop_nxt = prop & (m.getreg('input') == 0x0)
m.set_next('prop', prop_nxt)
# Set initial condition
m.set_init('prop', m.bool(True))
m.set_init('input', m.const(0x0, 16))
# Create golden model
golden = ila.Abstraction('golden')
g_prop = golden.bit('prop')
golden.set_next('prop', golden.bool(True))
golden.set_init('prop', golden.bool(True))
# Call bmc
print ila.bmc(10, m, prop, 1, golden, g_prop)
def test2():
m1 = ila.Abstraction('t1')
x1 = m1.reg('x', 8)
y1 = m1.reg('y', 8)
f = m1.fun('foo', 8, [8])
g = m1.fun('goo', 8, [8])
m1.set_next('x', x1)
m1.set_next('y', ila.appfun(f, x1))
assert m1.areEqualUnrolled(1, y1, ila.appfun(f, x1))
assert not m1.areEqualUnrolled(1, y1, ila.appfun(g, x1))
def model(paramsyn):
# create the alu.
alu = alu_sim()
sys = ila.Abstraction("alu")
sys.enable_parameterized_synthesis = paramsyn
# state elements.
rom = sys.mem('rom', alu.ROM_ADDR_WIDTH, alu.OPCODE_WIDTH)
pc = sys.reg('pc', alu.ROM_ADDR_WIDTH)
opcode = rom[pc]
regs = [sys.reg('r%d' % i, alu.REG_SIZE) for i in xrange(alu.NUM_REGS)]
# get the two sources.
imm = rom[pc + 1]
rs = ila.choice('rs', regs)
rt = ila.choice('rt', regs + [imm])
results = [rs + rt, rs - rt]
# golden model
gm_regs_next, pc_next = aluexpr(rom, pc, regs)
# set next for PC.
sys.set_next('pc', pc_next)
# rom never changes.
sys.set_next('rom', rom)
regs_next = []
for i in xrange(alu.NUM_REGS):
ri_next = ila.choice('result%d' % i, results + [regs[i]])
sys.set_next('r%d' % i, ri_next)
# set the fetch expressions.
sys.fetch_expr = opcode
# now set the decode expressions.
sys.decode_exprs = [opcode[5:0] == i for i in xrange(alu.NUM_CARE_OPCODES)]
# now synthesize.
st = time.clock()
#sys.synthesize(lambda s: alu.alusim(s))
sys.synthesize(lambda s: alu.alusim(s))
et = time.clock()
print '%.3f' % (et - st)
for i in xrange(alu.NUM_REGS):
rn1 = sys.get_next('r%d' % i)
rn2 = gm_regs_next[i]
if not sys.areEqual(rn1, rn2):
print rn1
print rn2
assert False
print rn1
sys.generateVerilog("syn.v")
def selfModel():
aes = ila.Abstraction('aesr')
key0 = aes.reg('in_key0',32)
key1 = aes.reg('in_key1',32)
key2 = aes.reg('in_key2',32)
key3 = aes.reg('in_key3',32)
state0 = aes.reg('state0',32)
state1 = aes.reg('state1',32)
state2 = aes.reg('state2',32)
state3 = aes.reg('state3',32)
i = aes.reg('i',4)
return aes
def readPy():
um = ila.Abstraction("aes1")
# init the state var.
# common state
state = um.reg('aes_state', 2)
opaddr = um.reg('aes_addr', 16)
oplen = um.reg('aes_len', 16)
keysel = um.reg('aes_keysel', 1)
ctr = um.reg('aes_ctr', 128)
key0 = um.reg('aes_key0', 128)
key1 = um.reg('aes_key1', 128)
xram = um.mem('XRAM', 16, 8)
aes = um.fun('aes', 128, [128, 128, 128])
# uinst state
rd_data = um.reg('rd_data', 128)
enc_data = um.reg('enc_data', 128)
byte_cnt = um.reg('byte_cnt', 16)
# state
state_next = readpyast(um, 'aes_state')
um.set_init('aes_state', um.const(1, 2))
um.set_next('aes_state', state_next)
# byte_cnt
byte_cnt_next = readpyast(um, 'byte_cnt')
um.set_next('byte_cnt', byte_cnt_next)
um.set_init('byte_cnt', um.const(0, 16))
# rd_data
rd_data_nxt = readpyast(um, 'rd_data')
um.set_next('rd_data', rd_data_nxt)
# enc_data
aes_key = ila.ite(keysel == 0, key0, key1)
aes_enc_data = ila.appfun(aes, [ctr, aes_key, rd_data])
enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data)
um.set_next('enc_data', enc_data_nxt)
# xram
uxram_nxt = readpyast(um, 'XRAM')
um.set_next('XRAM', uxram_nxt)
# the rest doesn't change.
um.set_next('aes_addr', opaddr)
um.set_next('aes_len', oplen)
um.set_ipred('aes_len', (oplen != 0) & (oplen[3:0] == 0))
um.set_next('aes_keysel', keysel)
um.set_next('aes_ctr', ctr)
um.set_next('aes_key0', key0)
um.set_next('aes_key1', key1)
return um
def main():
sys = ila.Abstraction("test")
r0 = sys.reg('r0', 8)
r1 = sys.reg('r1', 8)
a = sys.bit('a')
b = sys.bit('b')
ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1)
resfoo = sys.syn_elem("sum", ex, foo)
assert sys.areEqual(resfoo, r0 + r1)
resbar = sys.syn_elem("diff", ex, bar)
assert sys.areEqual(resbar, r0 - r1)
a1 = ila.choice("a1", a, ~a, a & b, a | b)
b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b])
a2 = ila.choice("a2", a, ~a)
b2 = ila.choice("b2", b, ~b)
t1 = a1 & b1
t2 = a2 & b2
y = t1 | t2
resbaz = sys.syn_elem("baz", y, baz)
assert sys.areEqual(resbaz, a ^ b)
resshaz = sys.syn_elem("shaz", y, shaz)
assert sys.areEqual(resshaz, ~(a ^ b))
c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8))
z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c)
resdaz = sys.syn_elem("daz", z, daz)
assert sys.areEqual(resdaz, r0 + r1 + 0x44)
slc0 = ila.readslice("r0slice", r0, 4)
slc1 = ila.readchunk("r1chunk", r1, 4)
res = ila.choice('slice', slc0 + slc1, slc0 - slc1)
resrmz = sys.syn_elem("razmatazz", res, razmatazz)
assert sys.areEqual(resrmz, r0[3:0] + r1[7:4])
nr0 = ila.writeslice("wr0slice", r0, slc0)
resjazz = sys.syn_elem("jazz", nr0, jazz)
assert sys.areEqual(resjazz, ila.concat(r0[3:0], r0[3:0]))
nr1 = ila.writechunk("wr0chunk", r0, slc0)
resjazy = sys.syn_elem("jazz", nr1, jazz)
assert sys.areEqual(resjazy, ila.concat(r0[3:0], r0[3:0]))
def createIla():
m = ila.Abstraction ('sha')
m.enable_parameterized_synthesis = 0
# input ports
cmd = m.inp ('cmd', 2)
cmdaddr = m.inp ('cmdaddr', 16)
cmddata = m.inp ('cmddata', 8)
# arch states
state = m.reg ('sha_state', 3)
rd_addr = m.reg ('sha_rdaddr', 16)
wr_addr = m.reg ('sha_wraddr', 16)
oplen = m.reg ('sha_len', 16)
rd_data = m.reg ('sha_rd_data', 512)
hs_data = m.reg ('sha_hs_data', 160)
xram = m.mem ('XRAM', 16, 8)
sha = m.fun ('sha', 160, [512])
# fetch is just looking at the input command.
m.fetch_expr = ila.concat ([state, cmd, cmdaddr, cmddata])
m.fetch_valid = (cmd == 1) | (cmd == 2)
# write commands.
def mb_reg_wr (name, reg):
# multibyte reg write.
reg_wr = ila.writechunk ('wr_' + name, reg, cmddata)
reg_nxt = ila.choice ('nxt_' + name, [reg_wr, reg])
m.set_next (name, reg_nxt)
mb_reg_wr ('sha_rdaddr', rd_addr)
mb_reg_wr ('sha_wraddr', wr_addr)
mb_reg_wr ('sha_len', oplen)
# state (atomic)
state_nxt = ila.choice ('state_nxt', [
m.const (0, 3), m.const (1, 3), m.const (2, 3),
m.const (3, 3), m.const (4, 3), state])
m.set_next ('sha_state', state_nxt)
# xram
xram_w_sha_little = ila.storeblk (xram, wr_addr, hs_data)
xram_w_sha_big = ila.storeblk_big (xram, wr_addr, hs_data)
xram_cho = ila.choice ('xram_nxt', xram, xram_w_sha_little, xram_w_sha_big)
xram_nxt = ila.ite ((state == 0) & (cmddata == 1), xram_cho, xram)
m.set_next ('XRAM', xram_nxt)
return m
def main():
c = ila.Abstraction("test")
a = c.reg('a', 8)
b = c.reg('b', 8)
r = a % b
for i in xrange(25):
av = random.randint(0, 0xff)
bv = random.randint(0, 0xff)
if bv == 0:
r = av
else:
r = av % bv
assump = (a == av) & (b == bv)
assert c.areEqual(assump, a % b, c.const(r, 8))
print '%02x %% %02x = %02x' % (av, bv, r)
def createPCRILA(synstates):
m = ila.Abstraction("sha")
inp = m.reg("input", 8)
inp1 = m.reg("input1", 8)
out = m.reg("output", 8)
m.set_next("output", ila.choice("out_choice", [inp, out]))
inp_dec = [inp == i for i in range(0, 512)]
inp1_dec = [inp1 == i for i in range(0, 512)]
out_dec = [out == i for i in range(0, 512)]
m.decode_exprs = inp_dec + inp1_dec + out_dec
m.synthesize("output", updateFifo)
ast = m.get_next("output")
m.exportOne(ast, "ast_out")
def modify():
# Create the ILA container.
m = ila.Abstraction('alu')
# Import the whole ILA from file.
m.importAll('ALU.ila')
# Completely define transition relations for unspecified states.
for i in xrange(0, 8):
regName = 'reg{}'.format(i)
m.set_next(regName, m.getreg(regName))
out_nxt = m.get_next('output')
inp_nxt = ila.concat(out_nxt, out_nxt)
m.set_next('input', inp_nxt)
# Export the result
m.exportAll('ALU_moore.ila')
def __init__(self):
self.model = ila.Abstraction("oc8051")
self.createInputs()
self.op0 = self.rom[self.pc]
self.op1 = self.rom[self.pc + 1]
self.op2 = self.rom[self.pc + 2]
self.opcode = ila.concat(self.op2, ila.concat(self.op1, self.op0))
self.dptr = ila.concat(self.dph, self.dpl)
self.cy = self.psw[7:7]
self.ac = self.psw[6:6]
self.ov = self.psw[2:2]
self._Rbank = self.psw[4:3]
self.rxaddr = [
ila.concat(self.model.const(0, 3),
ila.concat(self._Rbank, self.model.const(i, 3)))
for i in xrange(8)
]
self.rx = [self.iram[RxAddr_i] for RxAddr_i in self.rxaddr]
