def Exit(self, bound1, bound2, a1, a2, c1, c2, CrossAssumpt, CrossConclusion): ## For abs 1 checkRsFlag = True u1 = self.a1.newUnroller(self.ua1, setInitCondition=False) print 'Assuming:' invStr = ' AND '.join(['$%d' % idx for idx in range(len(a1))] + ['$$']) for idx, inv in enumerate(a1): print '$%d = %s' % (idx, inv) for inv in a1: u1.addAssumption(inv) print 'Unrolling...' u1.unrollTo(bound1) u1.addAssumption(~self.ua1.fetch_valid) print 'And also micro-program terminates: ', ~self.ua1.fetch_valid for idx, cond in enumerate(c1): print invStr + ' -> ' + str(cond) checkRsFlag = checkRsFlag and u1.checkAssertion(cond) ## For abs 2 u2 = self.a2.newUnroller(self.ua2, setInitCondition=False) print 'Assuming:' invStr = ' AND '.join(['$%d' % idx for idx in range(len(a2))] + ['$$']) for idx, inv in enumerate(a2): print '$%d = %s' % (idx, inv) for inv in a2: u2.addAssumption(inv) u2.unrollTo(bound2) u2.addAssumption(~self.ua2.fetch_valid) print 'And also: micro-prog ends $$: ', ~self.ua2.fetch_valid for idx, cond in enumerate(c2): print invStr + ' -> ' + str(cond) checkRsFlag = checkRsFlag and u2.checkAssertion(cond) ## Cross CrossAssumptList = [] for n1, n2 in CrossAssumpt: CrossAssumptList.append((1, n1, n2)) for n1, n2 in CrossConclusion: ila.enablelog("Unroller") ila.setloglevel(3, "info.txt") if ila.eqcheck(u1, u2, n1, n2, assumption=CrossAssumptList) == False: print 'left.{n1} = right.{n2} --/--> left.{n1} = right.{n2}'.format( n1=n1, n2=n2) checkRsFlag = False else: print 'left.{n1} = right.{n2} ==>> left.{n1} = right.{n2}, is valid'.format( n1=n1, n2=n2) return checkRsFlag
def main(): expFile = "tmp/test_ila_export.txt" sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0 + r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0 - r1) a1 = ila.choice("a1", a, ~a, a & b, a | b) b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a ^ b) resshaz = sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a ^ b)) c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8)) z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readslice("r1slice", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0] + r1[7:4]) sys.exportOne(resrmz, expFile) getback = sys.importOne(expFile) assert sys.areEqual(resrmz, getback) print getback #sys.exportFile(expFile); #sys.importFile(expFile); ila.setloglevel(3, "") ila.enablelog("Export") sys.exportList([resrmz, resdaz], expFile) l = sys.importList(expFile) for ast in l: print ast
def main(): iteAsNode = False iteAsNode = True hornFile = "tmp/horn_test_node.smt2" A = getDummyILA() ila.setloglevel(3, "") ila.enablelog("Horn") A.hornifyAll("tmp/horn_test_ILA.smt2") r2_nxt = A.get_next('r2') A.hornifyNode(r2_nxt, "r2_nxt") A.exportHornToFile(hornFile) m = ila.Abstraction("fun") x = m.reg('x', 8) y = m.reg('y', 16) f = m.fun('foo', 8, [8, 16]) r = ila.appfun(f, x, y) m.hornifyBvAsInt(True) m.hornifyNode(r, "foo") m.exportHornToFile(hornFile) alu = ila.Abstraction("alu") alu.hornifyBvAsInt(True) aluFile = 'tmp/alu.txt' if not os.path.exists(aluFile): print 'alu file not exist' return alu.importAll(aluFile) r0_nxt = alu.get_next('r0') r1_nxt = alu.get_next('r1') pc_nxt = alu.get_next('pc') rom_nxt = alu.get_next('rom') """ alu.hornifyNode(pc_nxt, "pc_nxt") alu.hornifyNode(r0_nxt, "r0_nxt") alu.hornifyNode(r1_nxt, "r1_nxt") alu.hornifyNode(rom_nxt, "rom_nxt") alu.exportHornToFile(hornFile) """ alu.addHornInstr('alu_instr', alu.bool(True)) alu.addHornNext('alu_instr', 'pc', pc_nxt) alu.addHornNext('alu_instr', 'r0', r0_nxt) alu.addHornNext('alu_instr', 'r1', r1_nxt) alu.addHornNext('alu_instr', 'rom', rom_nxt) alu.addHornChild('alu_child', 'alu_instr', alu.bool(True)) alu.addHornNext('alu_child', 'pc', pc_nxt) alu.addHornNext('alu_child', 'r0', r0_nxt) alu.addHornNext('alu_child', 'r1', r1_nxt) alu.addHornNext('alu_child', 'rom', rom_nxt) alu.generateHornMapping('Interleave') #alu.generateHornMapping ('Blocking') alu.exportHornToFile(hornFile)
def main(): ila.setloglevel(0, "") ila.enablelog ("ExportVerilog") parser = argparse.ArgumentParser() parser.add_argument("--numregs", type=int, default=2, help="# of registers") parser.add_argument("--regwidth", type=int, default=4, help="register width") parser.add_argument("--enable-param-syn", type=int, default=1, help="enable parameterized synthesis") args = parser.parse_args() numregs = args.numregs if (numregs & (numregs - 1)) != 0: print 'Error: number of registers must be power of two.' return model(numregs, args.regwidth, args.enable_param_syn)
def main(): ila.setloglevel(3, "") ila.enablelog("Z3ExprAdapter") c = ila.Abstraction("test") x = c.bit('x') y = c.bit('y') e1 = (x == y) e2 = ((x & y) | (~x & ~y)) assert c.areEqual(e1, e2) e1p = ~e1 e2p = ~e2 assert c.areEqual(e1p, e2p) assert not c.areEqual(e1p, e2) assert not c.areEqual(e1, e2p) e1 = (x & y) e2 = ~(~x | ~y) assert c.areEqual(e1, e2) assert not c.areEqual(e1, e1p) a = c.reg('a', 8) e1 = -a e2 = ~a + 1 e3 = ~a + 2 e4 = ila.choice("dummy", e2, e1) assert c.areEqual(e1, e2) assert c.areEqual(e1, e4) assert c.areEqual(e2, e4) assert not c.areEqual(e1, e3) assert not c.areEqual(e4, e3) bv1 = c.reg('bv1', 8) bv2 = c.reg('bv2', 8) bv_add1 = bv1 + bv2 bv_add2 = bv2 + bv1 assert c.areEqual(bv_add1, bv_add2)
import ila import time import pickle import Instruction_Format import re ila.setloglevel(3, '') ila.enablelog('BMCResult') ptx_declaration_obj = open('ptx_declaration_file', 'r') ptx_declaration = pickle.load(ptx_declaration_obj) program_obj = open('ptx_add_neighbor', 'r') program = pickle.load(program_obj) instruction_format = Instruction_Format.InstructionFormat() class barSpec(object): def __init__(self): self.BAR_INIT = 0 self.BAR_ENTER = 1 self.BAR_WAIT = 2 self.BAR_EXIT = 3 self.BAR_FINISH = 4 self.BAR_COUNTER_ENTER_BITS = 32 self.BAR_COUNTER_EXIT_BITS = 32 self.BAR_STATE_BITS = 3 self.THREAD_NUM = 2 self.BAR_OPCODE = 71 class ptxGPUModel(object): def __init__(self):
roundkeyA0 = aes.getreg('in_key0') roundkeyA1 = aes.getreg('in_key1') roundkeyA2 = aes.getreg('in_key2') roundkeyA3 = aes.getreg('in_key3') roundKeyB = aes.getreg('keyr1') roundENCA0 = aes.getreg('state0') roundENCA1 = aes.getreg('state1') roundENCA2 = aes.getreg('state2') roundENCA3 = aes.getreg('state3') roundENCB = aes.getreg('encr1') a1 = cat([roundkeyA0,roundkeyA1,roundkeyA2,roundkeyA3]) == roundKeyB a2 = cat([roundENCA0,roundENCA1,roundENCA2,roundENCA3]) == roundENCB print 'Round Key EQ:', print 'Pending...' print aes.bmcInit(assertion = a1, bound = 1, init = True) print 'Round Enc EQ:', print 'Pending...' print aes.bmcInit(assertion = a2, bound = 1, init = True) if __name__ == '__main__': ila.setloglevel(3,"") ila.enablelog("BMCResult") aesR = buildTwoModels() print 'built Complete.' checkEQ(aesR) print 'prove Complete.'
def main(): # ila.enablelog("Synthesizer") ila.enablelog("VerilogExport") ila.setloglevel(3,"") sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') out1 = sys.reg('Rsum',8) out2 = sys.reg('Rdiff',8) out3 = sys.bit('Rbaz') out4 = sys.bit('Rshaz') out5 = sys.reg('Rdaz',8) out6 = sys.reg('Rrazmatazz',4) out7 = sys.reg('Rjazz',8) mem = sys.mem('mem1',2,4) action1 = ila.store(mem,r0[1:0],r1[3:0]) action2 = ila.store(mem,r1[1:0],r0[3:0]) action3 = ila.store( ila.store(mem,r0[7:6],r1[7:4]) ,r1[7:6],r0[7:4] ) final_action = ila.ite(a,action1, ila.ite(b,action2,action3)) sys.set_next('mem1',final_action) ex = ila.choice("function", r0+r1, r0-r1, r0+r1+1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0+r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0-r1) a1 = ila.choice("a1", a, ~a, a&b, a|b) b1 = ila.choice("b1", [b, ~b, a&b, a|b, a^b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a^b) resshaz= sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a^b)) c = ila.inrange("cnst", sys.const(0x00,8), sys.const(0xff,8)) z = ila.choice("func_z", r0+r1+c, r0+r1-c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readchunk("r1chunk", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0]+r1[7:4]) nr0 = ila.writeslice("wr0slice", r0, slc0) resjazz = sys.syn_elem("jazz", nr0, jazz) assert sys.areEqual(resjazz, ila.concat(r0[3:0], r0[3:0])) sys.set_next('Rsum',resfoo) sys.set_next('Rdiff',resbar) sys.set_next('Rbaz',resbaz) sys.set_next('Rshaz',resshaz) sys.set_next('Rdaz',resdaz) sys.set_next('Rrazmatazz',resrmz) sys.set_next('Rjazz',resjazz) sys.generateVerilog(VerilogFile) testVerilog(VerilogFile)
for s in all_states: Npath = root + '/instr_R_%x/%s' % (addr, s) Nast = m.importOne(Npath) m.addHornNext(instrName, s, Nast) for st in all_child: Dpath = root + '/child_%d/decode' % st Dast = m.importOne(Dpath) childName = 'sha_u_%x' % st m.addHornChild(childName, 'sha_w_fe00', Dast) #m.hornifyNode (Dast, 'delta_%d' % st) for s in all_states: Npath = root + '/child_%d/%s' % (st, s) Nast = m.importOne(Npath) m.addHornNext(childName, s, Nast) #m.hornifyNode (Nast, 'N_%d_%s_nxt' % (st, s)) m.generateHornMapping('Interleave') ilaFile = destDir + '/ila.smt2' m.exportHornToFile(ilaFile) if __name__ == '__main__': ila.setloglevel(3, "") #ila.enablelog("Horn") ila.enablelog("Horn-Warning") ila.enablelog("Horn-Error") createHorn()
def model(num_regs, reg_size, paramsyn): reg_field_width = int(math.log(num_regs, 2)) assert (1 << reg_field_width) == num_regs # create the alu. alu = alu_sim(reg_field_width, reg_size) sys = ila.Abstraction("alu") sys.enable_parameterized_synthesis = paramsyn # state elements. rom = sys.mem('rom', alu.ROM_ADDR_WIDTH, alu.OPCODE_WIDTH) pc = sys.reg('pc', alu.ROM_ADDR_WIDTH) opcode = rom[pc] regs = [sys.reg('r%d' % i, alu.REG_SIZE) for i in xrange(alu.NUM_REGS)] # get the two sources. rs = ila.choice('rs', regs) rt = ila.choice('rt', regs) rs = [rs+rt, rs-rt, rs&rt, rs|rt, ~rs, -rs, ~rt, -rt] # set next. sys.set_next('pc', ila.choice('pc', pc+1, pc+2)) # set rom next. sys.set_next('rom', rom) regs_next = [] for i in xrange(alu.NUM_REGS): ri_next = ila.choice('result%d' % i, rs+[regs[i]]) sys.set_next('r%d' % i, ri_next) # set the fetch expressions. sys.fetch_expr = opcode # now set the decode expressions. sys.decode_exprs = [opcode == i for i in xrange(alu.NUM_OPCODES)] # synthesize pc first. sys.synthesize('pc', lambda s: alu.alusim(s)) pc_next = sys.get_next('pc') assert sys.areEqual(pc_next, pc+1) # now synthesize. st = time.clock() sys.synthesize(lambda s: alu.alusim(s)) et = time.clock() print 'time for synthesis: %.3f' % (et-st) regs_next = aluexpr(rom, pc, regs) for i in xrange(alu.NUM_REGS): rn1 = sys.get_next('r%d' % i) rn2 = regs_next[i] print '(a) r%d: %s' % (i, str(rn1)) print '(b) r%d: %s' % (i, str(rn2)) assert sys.areEqual(rn1, rn2) print '--> PC_NEXT:', sys.get_next('pc') #sys.add_assumption(opcode == 0x80) #print sys.syn_elem("r0", sys.get_next('r0'), alusim) # simplify PC. pc_next_p = ila.simplify(sys.bool(True), sys.get_next('pc')) sys.set_next('pc', pc_next_p) print '--> PC_NEXT:', sys.get_next('pc') expFile = "tmp/alu.txt" sys.exportAll(expFile); verilogFile = "tmp/alu.v" ila.setloglevel(3, "") ila.enablelog("VerilogExport") sys.generateVerilog(verilogFile) # now import into a new abstraction and check. sysp = ila.Abstraction("alu") sysp.importAll(expFile); romp = sysp.getmem('rom') pcp = sysp.getreg('pc') regsp = [sysp.getreg('r%d' % i) for i in xrange(alu.NUM_REGS)] regs_next = aluexpr(romp, pcp, regsp) for i in xrange(alu.NUM_REGS): rn1 = sysp.get_next('r%d' % i) rn2 = regs_next[i] assert sysp.areEqual(rn1, rn2)