def add_op(self, op: Instruction) -> bool: '''Returns true if the op was successfully added''' if not isinstance(op, Op): return False if op == '+': self._values[self._offset] += 1 elif op == '-': self._values[self._offset] -= 1 elif op == '>': self._offset += 1 self._required_right_room = max(self._required_right_room, self._offset) elif op == '<': self._offset -= 1 self._required_left_room = min(self._required_left_room, self._offset) elif op == '.': return False elif op == ',': return False elif op == '[': return False elif op == ']': return False else: assert False, 'Invalid operation ' + str(op) if self._values[self._offset] == 0: self._values.pop(self._offset) self._emulated_ops += 1 if self._span is None: self._span = op.span() self._span = self._span.extend_to(op.span()) return True
def generate_local_assign(self, assign: LocalAssignStmt): left = assign.left.name_list right = assign.right.expr_list # left -- add local variable # for name in left: # right -- calc value and assign to left variable for idx, name in enumerate(left): register = self.symbol_table.insert(name.value, name) # res = self.symbol_table.lookup(name.value) val = right[idx] res = self.generate_expr(register, val) if ExprEnum.BINOP == val.kind and BinOpEnum.AND == val.value.operator: self._back_path(val.false_list) elif ExprEnum.BINOP == val.kind and BinOpEnum.OR == val.value.operator: self._back_path(val.true_list) if res < 0 and (type(self.constant_pool.index(res)) == TermFalse or type(self.constant_pool.index(res)) == TermTrue): self.proto.add_instruction(Instruction(OpCode.LOADBOOL, register, 0 if type(self.constant_pool.index(res)) == TermFalse else 1)) else: # same register not generate opcode if register != res: self.proto.add_instruction(Instruction(OpCode.LOADK, register, res))
def __init__(self, memory_image, forwarding=False, debug=False): ''' Instantiate a new processor. ''' self.mem_image = copy.deepcopy(memory_image) self.original_mem = memory_image self.forwarding = forwarding self.debug = debug self.frwrd_dict = dict() self.regs = memory.registers() self.data_list = [ 0, Instruction(None), Instruction(None), Instruction(None), Instruction(None) ] self.pc = 0 self.arith_opcode = ['Add', 'Addi', 'Sub', 'Subi', 'Mul', 'Muli'] self.logic_opcode = ['Or', 'Ori', 'And', 'Andi', 'Xor', 'Xori'] self.ld_opcode = ['Ldw', 'Stw'] self.ctrl_opcode = ['Bz', 'Beq', 'Jr', 'Halt'] self.r_type = ['Add', 'Sub', 'Mul', 'Or', 'And', 'Xor'] self.reg_change = {} self.ari_count = 0 self.logic_count = 0 self.ctrl_count = 0 self.ld_count = 0 self.stall_cycle = 0 self.num_instructions = 0 self.hazards = 0 self.st_count = [] self.Halt = False self.cycles = 0
def _generate_equal_expr(self, register, opcode: OpCode, expr: BinOpExpr): left_reg = self.symbol_table.add_temp_var() self.generate_expr(left_reg, expr.left) right_reg = self.symbol_table.add_temp_var() self.generate_expr(right_reg, expr.right) self.proto.add_instruction(Instruction(opcode, 1, left_reg, right_reg)) self.proto.add_instruction(Instruction(OpCode.JMP, 0, 1)) self.proto.add_instruction(Instruction(OpCode.LOADBOOL, register, 1, 1)) self.proto.add_instruction(Instruction(OpCode.LOADBOOL, register, 0, 0))
def test_Task1(self): solver = AoC8() solver.data = [Instruction("nop", 0), Instruction("acc", 1), Instruction("jmp", 4), Instruction("acc", 3), Instruction("jmp", -3), Instruction("acc", -99), Instruction("acc", 1), Instruction("jmp", -4), Instruction("acc", 6)] count = solver.Task1() self.assertEqual(5, count)
def disassemble(self): pc = self.pc for word in self.ins: _ins = Instruction(word) if _ins.is_branch: _ins.ins["imm"] = pc+4 + _ins.ins["imm"]*4 elif _ins.is_jump: addr = _ins.ins["addr"] _ins.ins["addr"] = ((pc+4)&0xf0000000) | (addr << 2) print "0x%08x:\t%s" % (pc, _ins.ins_str()) pc += 4
def parse(self, handle): self.definitions = yaml.load(handle) for kind, instructions in self.definitions['instructions'].items(): for instruction, description, formats in instructions: Instruction.align(0x0f if kind == 'arithmetic' else 0x07) if kind == 'arithmetic': for modifier in ('', 's'): self.create_instruction(kind, instruction, description, formats, modifier, show_format = False) else: self.create_instruction(kind, instruction, description, formats, show_format = True)
class InstructionTest(unittest.TestCase): def setUp(self): self.instruction = Instruction("instruction inicial",False,False) self.instructionFinal = Instruction("instruction final y de io",True,True) def test_execute_noFinal(self): assert not self.instruction.execute() def test_execute_final(self): assert self.instructionFinal.execute()
def __init__(self, transpiler, opcode, params = []): self.transpiler = transpiler base = int(params[0].raw, 0) offset = int(params[1].raw, 0) if offset >= base: raise ValueError("Offset >= Base for align") cur_offset = transpiler.bpos % base if offset < cur_offset: offset += base self.align_len = offset - cur_offset Instruction.__init__(self, transpiler, opcode)
def generate_login_or_expr(self, register, expr: BinOpExpr): self.generate_expr(register, expr.left) # B1 or B2 => if B1 = false jump to B2 self.proto.add_instruction(Instruction(OpCode.TEST, register, 1)) # if B1 true jump to end self.proto.add_instruction(Instruction(OpCode.JMP, 0, 0)) # record left expr true list expr.left.true_list.append(self.proto.pc()) self.generate_expr(register, expr.right) # record right expr true list expr.right.true_list.append(self.proto.pc())
def decode(filename): binary_instructions = [] with open(filename, "rb") as file: while True: raw_bytes = file.read(4) # raw bytes to int int_val = int.from_bytes(raw_bytes, byteorder='big') if int_val == 0: break # int to binary string master_opcode = format( int_val, "b") # returns a string of format 10010001 (8 bits) # converting int to binary drops the leading zeros, so this adds them back if len(master_opcode) != 32: len_diff = 32 - len(master_opcode) zero_padding = "0" * len_diff master_opcode = zero_padding + master_opcode # creates all opcode versions with given 32 bit instruction opcode6 = master_opcode[:6].encode() opcode8 = master_opcode[:8].encode() opcode9 = master_opcode[:9].encode() opcode10 = master_opcode[:10].encode() opcode11 = master_opcode[:11].encode() # create a new instruction and set the values of it's opcode attributes new_instruction = Instruction() new_instruction.add_properties( opcode6=opcode6, opcode8=opcode8, opcode9=opcode9, opcode10=opcode10, opcode11=opcode11, ) find_instruction_name(new_instruction) if new_instruction.name is None: print("Error: Opcode Does Not Exist") exit(1) fill_format_values(master_opcode, new_instruction) binary_instructions.append(new_instruction) construct_assembly(new_instruction) file.close() return binary_instructions
def fetch(self): instrToFetch = self.state.instrBufferSize - len(self.state.instrBuffer) '''print "InstrBuffer has " + str(len(self.state.instrBuffer)) + " entries" print "There are " + str(self.state.instrBufferSize) + " total spaces" print "Need to fetch " + str(instrToFetch)''' for i in range(instrToFetch): instruction = Instruction(self.state.instructions[self.state.programCounter + i]) instruction.parse() #print "Grabbed instruction " + str(instruction) self.state.instrBuffer.append(instruction) self.state.programCounter += instrToFetch return
def main(): file = open("input.txt", mode="r", encoding="utf-8") wire1 = file.readline().strip().split(',') wire2 = file.readline().strip().split(',') pos = Point(1, 1) dic = {} for idx in range(len(wire1)): instr = Instruction(wire1[idx]) current = instr.count while current > 0: instr.mutatePos(pos) dic[pos.key()] = "1" current -= 1 pos = Point(1, 1) closest = -1 for idx in range(len(wire2)): instr = Instruction(wire2[idx]) current = instr.count while current > 0: current -= 1 instr.mutatePos(pos) if (pos.key() in dic): distance = abs(pos.x - 1) + abs(pos.y - 1) print('intersection distance', distance, 'on', pos.key()) if (closest == -1 or closest > distance): closest = distance print('closest intersection', closest)
def generate_login_and_expr(self, register, expr: BinOpExpr): self.generate_expr(register, expr.left) # B1 AND B2 => if B1 = true jump to B2 self.proto.add_instruction(Instruction(OpCode.TEST, register, 0)) # if B1 false jump to end self.proto.add_instruction(Instruction(OpCode.JMP, 0, 0)) jump_index = self.proto.pc() # record left expr false list expr.left.false_list.append(jump_index) self.generate_expr(register, expr.right) # record right expr true list jump_index = self.proto.pc() expr.right.false_list.append(jump_index)
def __init__(self): """Inicializa um objeto Armazenamento de Controle""" # Ler microprog.rom file_content = get_file_content("../bin/microprog.rom") self._cs_bytes = [ file_content["bytes"][i:i + 8] for i in range(0, file_content["size"], 8) ] # Indica a posicao atual sendo lida no armazenamento de controle self._cs_pos = 0 # Indica qual instrucao esta situada na posicao atual self._instruction = Instruction(self._cs_bytes[self._cs_pos])
def _generate_binary_common(self, opcode: OpCode, register, binop: BinOpExpr): left_reg = self.generate_expr(register, binop.left) right_reg = self.symbol_table.add_temp_var() right_reg = self.generate_expr(right_reg, binop.right) self.proto.add_instruction(Instruction(opcode, register, left_reg, right_reg)) self.symbol_table.pop_temp_var() return register
def line_to_instruction(self, s): # Conversion # remove endline words = s.replace("\n", "") words = words.split(" ") # ignore lines with less than 2 words if len(words) < 2: return None str_name = words[0].lower() str_value = words[1] num_name = str_to_name(str_name) num_value = str_to_value(str_value) # Error Checking if num_name is None: error("Invalid Instruction " + str_name) return None if num_value is None: error("Invalid Value " + str_value) return None return Instruction(num_name, num_value)
def HandleLine(self, line): loc = sum([x.Size() for x in self.instructions]) for replace,value in self.defines.iteritems(): line = re.sub(replace, value, line) if re.match("^\s*$", line) is not None: return try: m = re.match( r'''^\s*\.DEFINE\s*(?P<label>[_a-zA-Z0-9]+)\s*(?P<value>.*)$''', line) if m is not None: self.defines[m.group('label')] = m.group('value') return m = re.match( r'''^\s*\.STRING\s*(?P<label>[_a-zA-Z0-9]+)\s*(?P<str>".*")''', line) if m is not None: self.RegisterDataLabel(m.group('label'), eval(m.group('str'))) return m = re.match("^\s*(?P<label>[_a-zA-Z0-9]+):\.*$", line) if m is not None: self.RegisterLabel(m.group('label'), loc) return m = re.match("^\s*#.*$", line) if m is not None: return inst = Instruction.parseline(self, loc, line) self.instructions.append(inst) except Exception as e: return None
def execute(self): try: while True: instruction = Instruction.load() instruction.execute() except VMException as e: print e
def highest_latency(self, instrct, seq = 0, choices_set = None): priority = seq + 1 instrct.priority = priority deps = instrct.dep_set if choices_set: deps = deps.union(choices_set) if not deps: return if is_gen_graphviz: next_instrct = max(deps, key = lambda x: Instruction.get_latency(x[0])) else: next_instrct = max(deps, key = Instruction.get_latency) deps.remove(next_instrct) self.highest_latency(next_instrct[0], priority, deps)
def setUp(self): self.instruction = Instruction("instruction inicial",False,False) self.instructionFinal = Instruction("instruction final y de io",True,True)
def __init__(self, value): Instruction.__init__(self, value)
def preprocess(lines, mode): """ Go through our instruction list and replaces any pseudo-instructions with actual instructions. Differs from the standard MIPS assembler in that we keep register keywords ($zero instead of converting to $0) and that we don't change all numbers to decimal (we assume hex). """ processed = [] for line in lines: instr = Instruction(line) if mode == "MIPS": if instr.operation == "noop": instr.update("sll", "$zero", "$zero", "0x0") elif instr.operation == "mov": instr.update("add", instr.operand0, instr.operand1, "$zero") elif instr.operation == "clear": instr.update("add", instr.operand0, "$zero", "$zero") elif instr.operation == "not": instr.update("nor", instr.operand0, instr.operand1, "$zero") elif instr.operation == "li": val = int(instr.operand1, 16) if val < 65536: instr.update("addiu", instr.operand0, "$zero", instr.operand1) else: instr.update("lui", instr.operand0, num_upper(val), instr.operand2) processed.append(str(instr)) instr.update("ori", instr.operand0, instr.operand0, num_lower(val)) elif instr.operation == "bge": label = instr.operand2 instr.update("slt", "$at", instr.operand0, instr.operand1) processed.append(str(instr)) instr.update("beq", instr.operand0, "$zero", label) elif instr.operation == "bgt": label = instr.operand2 instr.update("slt", "$at", instr.operand1, instr.operand0) processed.append(str(instr)) instr.update("bne", instr.operand0, "$zero", label) elif instr.operation == "ble": label = instr.operand2 instr.update("slt", "$at", instr.operand1, instr.operand0) processed.append(str(instr)) instr.update("beq", instr.operand0, "$zero", label) elif instr.operation == "blt": label = instr.operand2 instr.update("slt", "$at", instr.operand0, instr.operand1) processed.append(str(instr)) instr.update("bne", instr.operand0, "$zero", label) elif instr.operation == "b": instr.update("beq", "$zero", "$zero", instr.operand0) elif instr.operation == "bal": instr.update("bgezal", "$zero", instr.operand0, instr.operand2) elif instr.operation == "blez": label = instr.operand1 instr.update("slt", "$at", "$zero", instr.operand0) processed.append(str(instr)) instr.update("beq", instr.operand0, instr.operand1, label) elif instr.operation == "bgtu": label = instr.operand2 instr.update("sltu", "$at", instr.operand1, instr.operand0) processed.append(str(instr)) instr.update("bne", instr.operand0, "$zero", label) elif instr.operation == "bgtz": label = instr.operand1 instr.update("slt", "$at", "$zero", instr.operand0) processed.append(str(instr)) instr.update("bne", instr.operand0, instr.operand1, label) elif instr.operation == "beqz": instr.update("beq", instr.operand0, "$zero", instr.operand1) elif instr.operation == "mul": output = instr.operand0 instr.update("mult", instr.operand1, instr.operand2, None) processed.append(str(instr)) instr.update("mflo", output, None, None) elif instr.operation == "div" or instr.operation == "rem": # add bne and break, like MARS, to check for no div by 0? output = instr.operand0 isrem = instr.operation == "rem" instr.update("div", instr.operand1, instr.operand2, None) processed.append(str(instr)) instr.update(["mflo", "mfhi"][int(isrem)], output, None, None) processed.append(str(instr)) elif mode == "ARM": if instr.operation == "nop": instr.update("mov", "r0", "r0", None) processed.append(str(instr)) return processed