def bench_dct_1d(): tdut = dct_1d(inputs, outputs, clock, reset, fract_bits, out_prec, N) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) inputs.data_valid.next = True for i in range(samples): for j in range(N): inputs.data_in.next = in_out_data.inputs[i][j] yield clock.posedge @instance def monitor(): outputs_count = 0 while(outputs_count != samples): yield clock.posedge yield delay(1) if outputs.data_valid: # convert flat signal to array of signals out_print(in_out_data.outputs[outputs_count], outputs.out_sigs) outputs_count += 1 raise StopSimulation return tdut, tbclk, tbstim, monitor
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) inputs.data_valid.next = True for i in range(samples): for j in range(N**2): inputs.out_sigs[j].next = in_out_data.inputs[i][j] yield clock.posedge @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while (outputs_count != samples): out_print(in_out_data.outputs[outputs_count], outputs.out_sigs, N) yield clock.posedge yield delay(1) outputs_count += 1 raise StopSimulation return tdut, tbclock, tbstim, monitor
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i-3] cb_s.next = exp_cb[i-3] cr_s.next = exp_cr[i-3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_out_data.inputs['red'][i] rgb.green.next = in_out_data.inputs['green'][i] rgb.blue.next = in_out_data.inputs['blue'][i] if ycbcr.data_valid == 1: for ycbcr_act, val in zip(('y', 'cb', 'cr'), (int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))): in_out_data.actual_outputs[ycbcr_act].append(val) yield clock.posedge print_results(in_out_data.inputs, in_out_data.expected_outputs, in_out_data.actual_outputs) raise StopSimulation return tbdut, tbclk, tbstim
def bench_entropycoder(): """This bench is used to test the functionality""" # instantiate module and clock inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) @instance def tbstim(): """stimulus generates inputs for entropy coder""" # reset the module yield pulse_reset(reset, clock) # send input test cases into the module for i in range(-2**(width_data-1)+1, 2**(width_data-1), 1): data_in.next = i yield clock.posedge yield clock.posedge # extract results from reference design amplitude_ref, size_ref = entropy_encode(int(data_in)) # comparing reference and module results assert size == size_ref assert amplitude == amplitude_ref raise StopSimulation return tbstim, inst, inst_clock
def bench_dct_2d(): tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, stage_1_prec, output_bits, N) tbclock = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) inputs.data_valid.next = True for i in range(samples): for j in in_out_data.inputs[i]: for k in j: inputs.data_in.next = k yield clock.posedge @instance def monitor(): outputs_count = 0 while outputs_count != samples: yield clock.posedge yield delay(1) if outputs.data_valid: out_print(in_out_data.outputs[outputs_count], outputs.out_sigs, N) outputs_count += 1 raise StopSimulation return tdut, tbclock, tbstim, monitor
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) inputs.data_valid.next = True for i in range(samples): for j in range(N**2): inputs.out_sigs[j].next = in_out_data.inputs[i][j] yield clock.posedge @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while(outputs_count != samples): out_print(in_out_data.outputs[outputs_count], outputs.out_sigs, N) yield clock.posedge yield delay(1) outputs_count += 1 raise StopSimulation return tdut, tbclock, tbstim, monitor
def bench_quant(): """instantiation of quantizer module and clock""" inst = quantizer(clock, reset, quanti_datastream, quant_ctrl, quanto_datastream) inst_clock = clock_driver(clock) @instance def tbstim(): """we send test cases here""" # reset the block before processing yield pulse_reset(reset, clock) # select Cb or Cr component color = component.y2_space # process Cb or Cr component yield quant_top_block_process( clock, quant_ctrl, color, quanto_datastream, quanti_datastream, quant_in, quant_rom, max_addr, 1) print ("===============================================") # select Y1 or Y2 component color = component.cr_space # process Cb or Cr component yield quant_top_block_process( clock, quant_ctrl, color, quanto_datastream, quanti_datastream, quant_in, quant_rom, max_addr, 1) raise StopSimulation return tbstim, inst, inst_clock
def bench_entropycoder(): """This bench is used to test the functionality""" # instantiate module and clock inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) @instance def tbstim(): """stimulus generates inputs for entropy coder""" # reset the module yield pulse_reset(reset, clock) # send input test cases into the module for i in range(-2 ** (width_data - 1) + 1, 2 ** (width_data - 1), 1): data_in.next = i yield clock.posedge yield clock.posedge # extract results from reference design amplitude_ref, size_ref = entropy_encode(int(data_in)) # comparing reference and module results assert size == size_ref assert amplitude == amplitude_ref raise StopSimulation return tbstim, inst, inst_clock
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i - 3] cb_s.next = exp_cb[i - 3] cr_s.next = exp_cr[i - 3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_out_data.inputs['red'][i] rgb.green.next = in_out_data.inputs['green'][i] rgb.blue.next = in_out_data.inputs['blue'][i] if ycbcr.data_valid == 1: for ycbcr_act, val in zip( ('y', 'cb', 'cr'), (int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))): in_out_data.actual_outputs[ycbcr_act].append(val) yield clock.posedge print_results(in_out_data.inputs, in_out_data.expected_outputs, in_out_data.actual_outputs) raise StopSimulation return tbdut, tbclk, tbstim
def bench_rle_conversion(): width = 6 constants = Constants(width_addr=width, width_data=12, max_write_cnt=63, rlength=4, size=width.bit_length()) clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) indatastream = InDataStream(constants.width_data) bufferdatabus = BufferDataBus( constants.width_data, constants.size, constants.rlength) rleconfig = RLEConfig(constants.max_write_cnt.bit_length()) width_dbuf = constants.width_data + constants.size + constants.rlength dfifo_const = Constants(width=width_dbuf, depth=constants.max_write_cnt + 1) inst = rlencoder( dfifo_const, constants, reset, clock, indatastream, bufferdatabus, rleconfig) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_quant(): """instantiation of quantizer module and clock""" inst = quantizer(clock, reset, quanti_datastream, quant_ctrl, quanto_datastream) inst_clock = clock_driver(clock) @instance def tbstim(): """we send test cases here""" # reset the block before processing yield pulse_reset(reset, clock) # select Cb or Cr component color = component.y2_space # process Cb or Cr component yield quant_top_block_process(clock, quant_ctrl, color, quanto_datastream, quanti_datastream, quant_in, quant_rom, max_addr, 1) print("===============================================") # select Y1 or Y2 component color = component.cr_space # process Cb or Cr component yield quant_top_block_process(clock, quant_ctrl, color, quanto_datastream, quanti_datastream, quant_in, quant_rom, max_addr, 1) raise StopSimulation return tbstim, inst, inst_clock
def bench_huffman(): """bench to test the functionality of RLE""" inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) @instance def tbstim(): """Huffman input tests given here""" # reset the stimulus before sending data in yield pulse_reset(reset, clock) bufferdatabus.buffer_sel.next = False # send y1 component into the module color = component.y1_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_y, runlength_test_y, vli_size_test_y, clock) print ("=======================================") # read y1 component from the double FIFO bufferdatabus.buffer_sel.next = True yield read_block(bufferdatabus, clock) print ("==============================") # send cb component into the module color = component.cb_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_cb, runlength_test_cb, vli_size_test_cb, clock) print ("==========================================") # read cb component from the double FIFO bufferdatabus.buffer_sel.next = False yield clock.posedge yield read_block(bufferdatabus, clock) print ("==============================") # send cr component into the module color = component.cr_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_cr, runlength_test_cr, vli_size_test_cr, clock) print ("============================") # read cr component from the double FIFO bufferdatabus.buffer_sel.next = True yield clock.posedge yield read_block(bufferdatabus, clock) print ("==============================") yield toggle_signal(huffmancntrl.sof, clock) raise StopSimulation return tbstim, inst_clock, inst
def bench_huffman(): """bench to test the functionality of RLE""" inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) @instance def tbstim(): """Huffman input tests given here""" # reset the stimulus before sending data in yield pulse_reset(reset, clock) bufferdatabus.buffer_sel.next = False # send y1 component into the module color = component.y1_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_y, runlength_test_y, vli_size_test_y, clock) print("=======================================") # read y1 component from the double FIFO bufferdatabus.buffer_sel.next = True yield read_block(bufferdatabus, clock) print("==============================") # send cb component into the module color = component.cb_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_cb, runlength_test_cb, vli_size_test_cb, clock) print("==========================================") # read cb component from the double FIFO bufferdatabus.buffer_sel.next = False yield clock.posedge yield read_block(bufferdatabus, clock) print("==============================") # send cr component into the module color = component.cr_space yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty, color, vli_test_cr, runlength_test_cr, vli_size_test_cr, clock) print("============================") # read cr component from the double FIFO bufferdatabus.buffer_sel.next = True yield clock.posedge yield read_block(bufferdatabus, clock) print("==============================") yield toggle_signal(huffmancntrl.sof, clock) raise StopSimulation return tbstim, inst_clock, inst
def bench_entropycoder(): inst = entropycoder(width, clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] print_sig_1 = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] in_sigs = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] @instance def tbstim(): inputs.data_valid.next = True for i in range(samples): for j in range(N**2): in_sigs[j].next = inputs_rom[i * (N**2) + j] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) input_assign = assign_array(inputs.out_sigs, in_sigs) @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while (outputs_count != samples): for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 yield clock.posedge raise StopSimulation return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
def bench_divider(): """The module where we pass tests into divider block""" # instantiation of clock and divider inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) @instance def tbstim(): """Test cases are given here""" # reset signal yield pulse_reset(reset, clock) list_output = [] list_output_ref = [] # all the possible tests from -2048 to 2048 given here for dividend_temp in range(-2**(width_data), 2**(width_data), 1): for divisor_temp in range(0, 256, 1): dividend.next = dividend_temp divisor.next = divisor_temp result = divider_ref(dividend_temp, divisor_temp) list_output_ref.append(result) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) # pop the zeroes stored in the list because of pipelining list_output.pop(0) list_output.pop(0) list_output.pop(0) list_output.pop(0) # compare reference design divider output with that of HDL divider for item1, item2 in zip(list_output, list_output_ref): print ("quotient %d quotient_ref %d" % (item1, item2)) assert item1 == item2 raise StopSimulation return tbstim, inst, inst_clock
def bench_divider(): """The module where we pass tests into divider block""" # instantiation of clock and divider inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) @instance def tbstim(): """Test cases are given here""" # reset signal yield pulse_reset(reset, clock) list_output = [] list_output_ref = [] # all the possible tests from -2048 to 2048 given here for dividend_temp in range(-2**(width_data), 2**(width_data), 1): for divisor_temp in range(0, 256, 1): dividend.next = dividend_temp divisor.next = divisor_temp result = divider_ref(dividend_temp, divisor_temp) list_output_ref.append(result) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) # pop the zeroes stored in the list because of pipelining list_output.pop(0) list_output.pop(0) list_output.pop(0) list_output.pop(0) # compare reference design divider output with that of HDL divider for item1, item2 in zip(list_output, list_output_ref): print("quotient %d quotient_ref %d" % (item1, item2)) assert item1 == item2 raise StopSimulation return tbstim, inst, inst_clock
def bench_bytestuffer(): """This bench is used to test the functionality""" # instantiate module and clock inst = bytestuffer(clock, reset, bs_in_stream, bs_out_stream, bs_cntrl, num_enc_bytes) inst_clock = clock_driver(clock) @instance def tbstim(): """stimulus generates inputs for byte stuffer""" # reset the module yield pulse_reset(reset, clock) yield toggle_signal(bs_cntrl.start, clock) yield clock.posedge # send input data for i in range(64): # send 0xFF bytes if i % 5 == 0: bs_in_stream.data_in.next = 0xFF # send other bytes else: bs_in_stream.data_in.next = i yield clock.posedge if bs_out_stream.data_valid: print("output data is %d" % bs_out_stream.byte) # assert fifo empty when all the inputs are over if i == 63: bs_in_stream.fifo_empty.next = True for _ in range(3): yield clock.posedge if bs_out_stream.data_valid: print("output data is %d" % bs_out_stream.byte) yield toggle_signal(bs_cntrl.sof, clock) # if last byte is 0xFF. Print the zero's stuffed if bs_out_stream.data_valid: print("output data is %d" % bs_out_stream.byte) print("total encoded bytes is %d" % num_enc_bytes) raise StopSimulation return tbstim, inst, inst_clock
def bench_rle_core(): """The conversion module for rle core""" inst = rle( clock, reset, datastream, rlesymbols, rleconfig ) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy inputs for conversion purpose""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_frontend(): tdut = frontend_top_level_v2(inputs, outputs, clock, reset) tbclock = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) inputs.data_valid.next = True for i in range(samples): for n in range(3): for j in range(N): for k in range(N): inputs.red.next = in_out_data.inputs[i][0][j][k] inputs.green.next = in_out_data.inputs[i][1][j][k] inputs.blue.next = in_out_data.inputs[i][2][j][k] yield clock.posedge @instance def monitor(): samples_count = 0 outputs_count = 0 outputs_list = [] clock_cycle_counter = 0 while(outputs.data_valid == False): yield clock.posedge clock_cycle_counter += 1 while samples_count != samples: print("Processing Block %d" %(samples_count+1)) for i in range(3): while(outputs_count != 64): outputs_list.append(int(outputs.data_out)) outputs_count += 1 clock_cycle_counter += 1 yield clock.posedge out_print(in_out_data.outputs[samples_count], outputs_list, N, i) outputs_count = 0 outputs_list = [] samples_count += 1 print("Clock Cycles taken for the block conversion:", clock_cycle_counter) raise StopSimulation return tdut, tbclock, tbstim, monitor
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = bytestuffer(clock, reset, bs_in_stream, bs_out_stream, bs_cntrl, num_enc_bytes) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] in_sigs = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): inputs.data_valid.next = True for i in range(samples): for j in range(N**2): in_sigs[j].next = inputs_rom[i*(N**2) + j] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) input_assign = assign_array(inputs.out_sigs, in_sigs) @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while(outputs_count != samples): for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 yield clock.posedge raise StopSimulation return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
def bench_dct_2d(): tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits, stage_1_prec, N) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): yield reset.negedge inputs.data_valid.next =True for i in range(samples * (N**2)): inputs.data_in.next = inputs_rom[i] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) @instance def monitor(): outputs_count = 0 while outputs_count != samples: yield clock.posedge if outputs.data_valid: for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 raise StopSimulation return tdut, tbclk, tbstim, monitor, tbrst, print_assign
def bench_doublebuffer_conversion(): """test bench for conversion""" clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) buffer_sel = Signal(bool(0)) width_data = 20 width_depth = 64 # instantiation of fifo-bus, clock and rledoublefifo dfifo_bus = FIFOBus(width=width_data) inst = doublefifo(clock, reset, dfifo_bus, buffer_sel, depth=width_depth) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """some tests for conversion purpose""" # select first buffer buffer_sel.next = False yield clock.posedge # write first data into double buffer dfifo_bus.write.next = True # convert signed number to unsigned dfifo_bus.write_data.next = 3 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_frontend(): print_sig = Signal(intbv(0, min=-outputs.out_range, max=outputs.out_range)) tdut = frontend_top_level_v2(inputs, outputs, clock, reset) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge inputs.data_valid.next = True for i in range(samples): for n in range(3): for j in range(64 * i, 64 * (i + 1)): inputs.red.next = r_rom[j] inputs.green.next = g_rom[j] inputs.blue.next = b_rom[j] yield clock.posedge @instance def monitor(): samples_count = 0 outputs_count = 0 clock_cycle_counter = 0 yield outputs.data_valid.posedge while(samples_count < samples): print("Processing Block %d" % (samples_count)) for i in range(3): while(outputs_count != 64): if i == 0: print_sig.next = y_out_rom[outputs_count + samples_count*64] elif i == 1: print_sig.next = cb_out_rom[outputs_count + samples_count*64] else: print_sig.next = cr_out_rom[outputs_count + samples_count*64] yield delay(1) print("%d %d" % (outputs.data_out, print_sig)) outputs_count += 1 clock_cycle_counter += 1 yield clock.posedge outputs_count = 0 samples_count += 1 raise StopSimulation return tdut, tbclock, tbstim, monitor, tbrst
def bench_dct_2d(): tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits, stage_1_prec, N) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): yield reset.negedge inputs.data_valid.next =True for i in range(samples * (N**2)): inputs.data_in.next = inputs_rom[i] yield clock.posedge print_assign = outputs.assignment_2(print_sig_1) @instance def monitor(): outputs_count = 0 while outputs_count != samples: yield clock.posedge if outputs.data_valid: for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 raise StopSimulation return tdut, tbclk, tbstim, monitor, tbrst, print_assign
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_backend_conversion(): """This bench is used to test the functionality""" # instantiate module and clock inst = backend(clock, reset, start_block, data_in, write_addr, valid_data, data_out, ready, addr, num_enc_bytes) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """testbench for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_quant_top_core(): """wrapper used for conversion purpose""" # instantiatiom of quantizer, clock and reset inst = quantizer(clock, reset, quanti_datastream, quant_ctrl, quanto_datastream) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests to convert the module""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_quant_core(): """wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = quantizer_core(clock, reset, quant_output_stream, quant_input_stream, color_component) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" data_in.next = 7 yield clock.posedge yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" data_in.next = 7 yield clock.posedge yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_rle_conversion(): """This bench is meant for conversion purpose""" # clock and reset signals clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # width of input data width_data = 12 # width of address bus width_addr = 6 # width to store the size width_size = width_data.bit_length() width_runlength = 4 # input data bus for rle module datastream = DataStream(width_data, width_addr) assert isinstance(datastream, DataStream) # connections between output symbols bufferdatabus = BufferDataBus(width_data, width_size, width_runlength) assert isinstance(bufferdatabus, BufferDataBus) # selects the color component, manages address values rleconfig = RLEConfig() assert isinstance(rleconfig, RLEConfig) inst = rlencoder(clock, reset, datastream, bufferdatabus, rleconfig) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """testbench for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_doublebuffer_conversion(): """test bench for conversion""" clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) buffer_sel = Signal(bool(0)) width_data = 20 width_depth = 64 # instantiation of fifo-bus, clock and rledoublefifo dfifo_bus = FIFOBus(width=width_data) inst = doublefifo( clock, reset, dfifo_bus, buffer_sel, depth=width_depth) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """some tests for conversion purpose""" # select first buffer buffer_sel.next = False yield clock.posedge # write first data into double buffer dfifo_bus.write.next = True # convert signed number to unsigned dfifo_bus.write_data.next = 3 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_doublebuffer_conversion(): """ test bench """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) width = 20 dfifo_bus = DoubleFifoBus(width=width) inst = doublefifo(clock, reset, dfifo_bus, width=width, depth=64) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_quant_core(): """instantiation of quantizer core module and clock signals""" inst = quantizer_core( clock, reset, quant_output_stream, quant_input_stream, color_component) inst_clock = clock_driver(clock) @instance def tbstim(): """We send the inputs from here""" # reset the module before sending inputs yield pulse_reset(reset, clock) # select Cb or Cr component color = component.y2_space # process the component selected yield quant_block_process( clock, color_component, color, quant_in, quant_rom, quant_input_stream, quant_output_stream, max_addr) yield clock.posedge print ("====================================") # select Y1 or Y2 component color = component.cb_space # process the component selected yield quant_block_process( clock, color_component, color, quant_in, quant_rom, quant_input_stream, quant_output_stream, max_addr) yield clock.posedge raise StopSimulation return tbstim, inst, inst_clock
def bench_color_trans(): tbdut = rgb2ycbcr_v2(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): for j in range(3): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] rgb.color_mode.next = j yield clock.posedge @instance def monitor(): samples_count = 0 yield ycbcr.data_valid.posedge yield delay(1) while samples_count != samples: for i in range(3): if i == 0: print_sig.next = exp_y[samples_count] elif i == 1: print_sig.next = exp_cb[samples_count] else: print_sig.next = exp_cr[samples_count] yield delay(1) print("%d %d" % (ycbcr.data_out, print_sig)) yield clock.posedge samples_count += 1 raise StopSimulation return tbdut, tbclk, tbstim, monitor, tbrst
def bench_quant_core(): """instantiation of quantizer core module and clock signals""" inst = quantizer_core(clock, reset, quant_output_stream, quant_input_stream, color_component) inst_clock = clock_driver(clock) @instance def tbstim(): """We send the inputs from here""" # reset the module before sending inputs yield pulse_reset(reset, clock) # select Cb or Cr component color = component.y2_space # process the component selected yield quant_block_process(clock, color_component, color, quant_in, quant_rom, quant_input_stream, quant_output_stream, max_addr) yield clock.posedge print("====================================") # select Y1 or Y2 component color = component.cb_space # process the component selected yield quant_block_process(clock, color_component, color, quant_in, quant_rom, quant_input_stream, quant_output_stream, max_addr) yield clock.posedge raise StopSimulation return tbstim, inst, inst_clock
def bench_color_trans(): tbdut = rgb2ycbcr_v2(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) rgb.data_valid.next = True for i in range(samples): for j in range(3): # rgb signal assignment in the dut rgb.red.next = in_out_data.inputs['red'][i] rgb.green.next = in_out_data.inputs['green'][i] rgb.blue.next = in_out_data.inputs['blue'][i] rgb.color_mode.next = j yield clock.posedge @instance def monitor(): samples_count = 0 output_list = [] yield ycbcr.data_valid.posedge yield delay(1) while samples_count != samples: for i in range(3): output_list.append(int(ycbcr.data_out)) yield clock.posedge yield delay(1) print_results(in_out_data.expected_outputs, output_list, samples_count) output_list = [] samples_count += 1 raise StopSimulation return tbdut, tbclk, tbstim, monitor
def bench_entropycoder(): inst = entropycoder(width, clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) @instance def tbstim(): """stimulus generates inputs for entropy coder""" yield pulse_reset(reset, clock) for i in range(-2**(width-1), 2**(width-1), 1): data_in.next = i yield clock.posedge yield clock.posedge amplitude_ref, size_ref = entropy_encode(int(data_in)) # comparing with the data present in reference assert size == size_ref assert amplitude == amplitude_ref raise StopSimulation return tbstim, inst, inst_clock
def bench_rle_core(): """The RLE Core is tested in this block""" # instantiation of the rle core inst = rle( clock, reset, datastream, rlesymbols, rleconfig ) # clock instantiation inst_clock = clock_driver(clock) @instance def tbstim(): """Test inputs given here""" # reset before sending data yield pulse_reset(reset, clock) # components of type y1 or y2 processed yield block_process( clock, red_pixels_1, datastream, rlesymbols, rleconfig, component.y1_space, max_count=max_addr_cnt ) print ("======================") # components of type y1 or y2 processed yield block_process( clock, red_pixels_2, datastream, rlesymbols, rleconfig, component.y2_space, max_count=max_addr_cnt ) print ("=====================") # components of type cb processes yield block_process( clock, green_pixels_1, datastream, rlesymbols, rleconfig, component.cb_space, max_count=max_addr_cnt ) print ("=====================") # components od type cb processed yield block_process( clock, green_pixels_2, datastream, rlesymbols, rleconfig, component.cb_space, max_count=max_addr_cnt ) print ("=====================") # components of type cr processed yield block_process( clock, blue_pixels_1, datastream, rlesymbols, rleconfig, component.cr_space, max_count=max_addr_cnt ) print ("=====================") # components of type cr processed yield block_process( clock, blue_pixels_2, datastream, rlesymbols, rleconfig, component.cr_space, max_count=max_addr_cnt ) print ("=====================") # start of new frame asserts rleconfig.sof.next = True yield clock.posedge raise StopSimulation return tbstim, inst_clock, inst
def bench_doublebuffer(): """This bench is used to send test cases into module""" # instantiation of clock and reset clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # buffer selection port instantiation buffer_sel = Signal(bool(0)) # input data width and depth of FIFO(double) width_data = 20 width_depth = 64 # instantiation of FIFOBus, clock and rledoublefifo dfifo_bus = FIFOBus(width=width_data) inst = doublefifo( clock, reset, dfifo_bus, buffer_sel, depth=width_depth) inst_clock = clock_driver(clock) @instance def tbstim(): """write data inputs to double buffer""" print("start simulation") # disable read and write dfifo_bus.write.next = False dfifo_bus.read.next = False # reset before sending data yield pulse_reset(reset, clock) # check if FIFO is empty assert dfifo_bus.empty # select first buffer buffer_sel.next = False yield clock.posedge # write first data into double buffer dfifo_bus.write.next = True # convert signed number to unsigned dfifo_bus.write_data.next = -1 and 0xFF yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty # write data into double buffer dfifo_bus.write.next = True dfifo_bus.write_data.next = 0xA1 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty # write data into rle double buffer dfifo_bus.write.next = True dfifo_bus.write_data.next = 0x11 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge # write data into rle double buffer dfifo_bus.write.next = True dfifo_bus.write_data.next = 0x101 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge # write data into rle double buffer for test_cases in range(64): if test_cases < 28: buffer_sel.next = False yield clock.posedge else: buffer_sel.next = True yield clock.posedge dfifo_bus.write.next = True dfifo_bus.write_data.next = test_cases yield clock.posedge dfifo_bus.write.next = False yield clock.posedge # read data from rle double buffer dfifo_bus.read.next = True yield clock.posedge assert dfifo_bus.read_data and -1 == -1 dfifo_bus.read.next = False buffer_sel.next = True yield clock.posedge # read data from rle double buffer dfifo_bus.read.next = True yield clock.posedge assert dfifo_bus.read_data == 0xA1 dfifo_bus.read.next = False buffer_sel.next = True yield clock.posedge # read data from rle double buffer dfifo_bus.read.next = True yield clock.posedge assert dfifo_bus.read_data == 0x11 dfifo_bus.read.next = False buffer_sel.next = True yield clock.posedge # read data from rle double buffer dfifo_bus.read.next = True yield clock.posedge assert dfifo_bus.read_data == 0x101 dfifo_bus.read.next = False # read data from rle double buffer for test_cases in range(64): if test_cases < 28: buffer_sel.next = True yield clock.posedge else: buffer_sel.next = False yield clock.posedge dfifo_bus.read.next = True yield clock.posedge assert dfifo_bus.read_data == test_cases dfifo_bus.read.next = False yield clock.posedge assert dfifo_bus.empty raise StopSimulation return inst, inst_clock, tbstim
def bench_rle(): """bench to test the functionality of RLE""" # clock and reset signals clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # color component class component = Component() assert isinstance(component, Component) # width of the input data width_data = 12 # width of the address register width_addr = 6 # width of the register to store size width_size = width_data.bit_length() # width to store the runlength width_runlength = 4 # input data stream into the register datastream = DataStream(width_data, width_addr) assert isinstance(datastream, DataStream) # connection between rlecore output bus and Double FIFO bufferdatabus = BufferDataBus(width_data, width_size, width_runlength) assert isinstance(bufferdatabus, BufferDataBus) # selects the color component, manages start and ready values rleconfig = RLEConfig() assert isinstance(rleconfig, RLEConfig) # instantiation for clock and rletop module inst = rlencoder(clock, reset, datastream, bufferdatabus, rleconfig) inst_clock = clock_driver(clock) @instance def tbstim(): """RLE input tests given here""" # reset the stimulus before sending data in yield pulse_reset(reset, clock) # write y1 component into 1st buffer bufferdatabus.buffer_sel.next = False yield clock.posedge yield write_block( clock, red_pixels_1, datastream, rleconfig, component.y1_space ) yield clock.posedge print ("============================") # read y1 component from 1st Buffer yield read_block(True, bufferdatabus, clock) # write y2 component into 2nd Buffer yield write_block( clock, red_pixels_2, datastream, rleconfig, component.y2_space ) yield clock.posedge print ("============================") # read y2 component from 2nd Buffer yield read_block(False, bufferdatabus, clock) # write cb Component into 1st Buffer yield write_block( clock, green_pixels_1, datastream, rleconfig, component.cb_space ) yield clock.posedge print ("=============================") # read cb component from 1st Buffer yield read_block(True, bufferdatabus, clock) # write cb Component into 2nd Buffer yield write_block( clock, green_pixels_2, datastream, rleconfig, component.cb_space ) yield clock.posedge print ("==============================") # read cb component from 2nd Buffer yield read_block(False, bufferdatabus, clock) # write cr Component into 1st Buffer yield write_block( clock, blue_pixels_1, datastream, rleconfig, component.cr_space ) yield clock.posedge print ("==============================") # read cr component from 1st Buffer yield read_block(True, bufferdatabus, clock) # write cr Component into 2nd Buffer yield write_block( clock, blue_pixels_2, datastream, rleconfig, component.cr_space ) yield clock.posedge print ("==============================") # read cr component from 1st Buffer yield read_block(False, bufferdatabus, clock) print ("==============================") # end of stream when sof asserts yield clock.posedge rleconfig.sof.next = True yield clock.posedge raise StopSimulation return tbstim, inst_clock, inst
def bench_backend(): """This bench is used to test the functionality""" # instantiate module and clock inst = backend(clock, reset, start_block, data_in, write_addr, valid_data, data_out, ready, addr, num_enc_bytes) inst_clock = clock_driver(clock) @instance def tbstim(): """stimulus generates inputs for entropy coder""" # reset the module output_model = [0] * 64 yield pulse_reset(reset, clock) # write Y data into input buffer valid_data.next = True yield clock.posedge write_addr.next = 64 for i in range(64): data_in.next = i % 25 yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge for _ in range(35): yield clock.posedge # start the blocks yield toggle_signal(start_block, clock) # write Cb data into input buffer valid_data.next = True yield clock.posedge for i in range(64): data_in.next = i % 16 yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge while not ready: yield clock.posedge yield toggle_signal(start_block, clock) # write Cr data into input buffer valid_data.next = True yield clock.posedge for i in range(64): data_in.next = i % 47 yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge while not ready: yield clock.posedge yield toggle_signal(start_block, clock) # write Y data into input buffer valid_data.next = True yield clock.posedge for i in range(64): data_in.next = i % 28 yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge while not ready: yield clock.posedge yield toggle_signal(start_block, clock) # write Cb data into input buffer valid_data.next = True yield clock.posedge for i in range(64): data_in.next = i % 40 index = int(addr) output_model[index] = int(data_out) yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge yield toggle_signal(start_block, clock) # write Cr data into input buffer valid_data.next = True yield clock.posedge for i in range(64): data_in.next = i % 31 index = int(addr) output_model[index] = int(data_out) yield clock.posedge write_addr.next = write_addr + 1 valid_data.next = False yield clock.posedge while not ready: yield clock.posedge yield toggle_signal(start_block, clock) while not ready: index = int(addr) output_model[index] = int(data_out) yield clock.posedge yield toggle_signal(start_block, clock) while not ready: index = int(addr) output_model[index] = int(data_out) yield clock.posedge yield toggle_signal(start_block, clock) while not ready: index = int(addr) output_model[index] = int(data_out) yield clock.posedge yield toggle_signal(start_block, clock) while not ready: index = int(addr) output_model[index] = int(data_out) yield clock.posedge print("===================") for i in range(addr): print("outputs_hdl %d" % output_model[i]) print("======================") # get outputs from reference values output_ref = [] output_ref = backend_soft() for i in range(len(output_ref)): print("outputs_soft %d" % int(output_ref[i], 2)) print("===========================") # compare reference and HDL outputs for i in range(len(output_ref)): assert int(output_ref[i], 2) == output_model[i] raise StopSimulation return tbstim, inst, inst_clock