from string import Template
import os


def settings_path():
    os.environ["STILDPV_HOME"] = "/cad/Synopsys/TetraMax/E-2010.12-SP2/linux/stildpv/"


if __name__ == "__main__":
    target = "b10"
    stil_f = target + ".stil"
    si_f = target + ".test_si"
    output_f = target + ".xfill_stil"

    os.chdir(".temp/")  # よくわからないファイルが出るので作業ディレクトリの変更
    pattern = SortMinTransition.extract_pattern(stil_f)

    f_pattern = []
    with open(si_f, "r") as f:
        for line in f.readlines():
            print(line)
            f_pattern.append(line.split(" ")[1][:-1])

    for i in range(len(f_pattern)):
        pattern[i]["test_si"] = f_pattern[i]

    output = SortMinTransition.make_initial(stil_f)
    output.extend(SortMinTransition.pattern_to_file(pattern))
    output.extend(SortMinTransition.make_after(stil_f))
    # print(output)
    with open(output_f, "w") as f:
Example #2
0
def get_sdql_with_p(settings):
    num = SortMinTransition.pattern_num(settings["stil"])
    for i in range(num):
        settings["last_p"] = i + 1
        request_SDQL_with_p(settings)
Example #3
0
from lib.synopsys import Synopsys
from lib.sort_min_transition import SortMinTransition
from string import Template
import os

def settings_path():
    os.environ["STILDPV_HOME"] = "/cad/Synopsys/TetraMax/E-2010.12-SP2/linux/stildpv/"

if __name__ == '__main__':
    target   = 'b10'
    os.chdir('.temp/')  # よくわからないファイルが出るので作業ディレクトリの変更


    # ランダム割り当て
    stil_f = target + '.stil'
    output_f = target + '.randomoptimise.stil'
    SortMinTransition.random_optimise(stil_f, output_f)

    # 単純にX割り当て
    stil_f = target + '.stil'
    output_f = target + '.xoptimise.stil'
    SortMinTransition.x_optimise(stil_f, output_f)

    # X割り当て
    stil_f = target + '.xfill_stil'
    output_f = target + '.proposexoptimise.stil'
    SortMinTransition.x_optimise(stil_f, output_f)
Example #4
0
def trans_both(settings):
    target = settings['name']
    print(SortMinTransition.trans(target + '.stil'))
    print(SortMinTransition.trans(target + '_sorted.stil'))
Example #5
0
def x_filling(settings):
    target = settings['name']
    SortMinTransition.x_optimise(target + '.stil', target + '_x.stil')
    SortMinTransition.random_optimise(target + '.stil', target + '_random.stil')
Example #6
0
def analysys_power_both(settings):
    analysys_power(settings)
    target = settings['name']
    SortMinTransition.sort(target + '.stil', target + '_sorted.stil')
    analysys_power_f(settings, target + '_sorted.stil')
Example #7
0
    try:
        os.mkdir(target)
    except:
        pass;
    # vgファイルから組み合わせ回路を抜き出し,vgファイルに戻す
    Verilog.convert_verilog_to_json(target + '.vg', output_f= target + '.json')
    Verilog.extract_comb_circuit_from_verilog_json(target + '.json', target + '.json')
    Verilog.convert_json_to_verilog(target + '.json', output_f=target + '_comb.vg')
    before_num = -1

    # 開始するパターン数の指定
    start_pattern = 545

    pattern_num = 0
    # scan_inの抽出
    for pattern in SortMinTransition.extract_pattern(target + '.stil'):
        already_fault_stuck = []
        script = []
        pattern_num += 1
        if pattern_num < start_pattern:
            continue
        input_pattern = pattern['test_si'].replace('N', 'x')
        try:
            os.remove(target + '_comb.stil')
        except:
            pass
        try:
            os.remove(target + '_test.v')
        except:
            pass
Example #8
0
if __name__ == '__main__':
    target = 'b05'

    os.chdir('.temp')  # よくわからないファイルが出るので作業ディレクトリの変更
    settings_path()

    settings = dict(nangate_db = '../data/Nangate/nangate45nm.db',
                    nangate_v  = '../data/Nangate/nangate.v',
                    name       = target,
                    clock      = clock_judge(target),
                    vhd        = '../data/ITC99/' + target + '.vhd',
                    vg         = target + '.vg',
                    spf        = target + '.spf',
                    stil       = target + '.stil',
                    slk        = target + '.slk',
                    stilcsv    = target + '.stilcsv',
                    vcd        = target + '.vcd',
                    fault      = target + '_report_faults.txt',
                    power      = target + '_report_power',
                    first_p    = 1,
                    last_p     = 1
                    )

    settings['stil'] = target + '.proposexoptimise.stil'
    num = SortMinTransition.pattern_num(settings['stil'])
    for i in range(num):
        settings['last_p'] = i + 1
        os.system('echo ' + str(settings['last_p']) + ' >> ' + settings['stil'] + '.sdql')
        Synopsys.system(shell='tmax', script='../template/RequestSDQL_with_p', context=settings)
Example #9
0
def get_pattern(pattern_num, pattern):
    already_fault_stuck = []
    script = []
    pattern_num = str(pattern_num)
    input_pattern = pattern['test_si'].replace('N', 'x')
    try:
        os.remove(target + '_comb.stil')
    except:
        pass
    try:
        os.remove(target + '_test.v')
    except:
        pass

    while True:
        print('-------------------------')
        print('input :' + input_pattern)
        script.append("ppi_ps_reg = " + str(len(input_pattern)) + "'b" +input_pattern + ';')
        script.append('$monitor("%b", ppo_ps_reg);')
        script.append('#100 $finish;')
        Verilog.convert_json_test_bench('../' + target + '.json', script_l=script, output_f=target + '_test.v')
        script = []

        # vcs の 実行
        STILDPV_HOME = "/cad/Synopsys/TetraMax/E-2010.12-SP2/linux/stildpv"
        DPV_FILE = target + '_test.v'
        NETLIST_FILES = '../' + target + '_comb.vg'
        LIB_FILES = '-v ../../data/Nangate/nangate.v'
        output = subprocess.check_output('vcs -R +acc+2 +vcs+lic+wait -P ' + STILDPV_HOME + '/lib/stildpv_vcs.tab +tetramax +delay_mode_zero ' \
                + DPV_FILE + ' ' + NETLIST_FILES + ' '  + LIB_FILES + ' ' + STILDPV_HOME + '/lib/libstildpv.a', shell=True, stderr=subprocess.STDOUT)
        output_pattern = re.search('[x01]{' + str(len(pattern['test_si'])) + '}', str(output)).group(0)


        print('output:' + output_pattern)

        # 入力の制約付きのPINを求める
        constraints_pin_dict = {}
        pin_num = 0
        for i_p, o_p in zip(input_pattern, output_pattern):
            # if i_p == 'x' and o_p == 'x':
            # if i_p == 'x' and o_p != 'x': 両方パス
            # 制約でi_pをo_pの値にしてもいいがそれによって出力が変わる可能性があるのでpass
            if i_p != 'x' and o_p == 'x':
                constraints_pin_dict[pin_num] = i_p;
            elif i_p != 'x' and o_p != 'x':
                constraints_pin_dict[pin_num] = i_p;
            pin_num += 1
        pi_constraints = ''
        for pin_num, pin_value in constraints_pin_dict.items():
            pi_constraints += 'add_pi_constraints ' + pin_value + ' ppi_ps_reg[' + str(pin_num) + ']\n'
        #print(pi_constraints)

        # 故障の設定
        # 問題点,最初の入力が優先されてしまうため,無限ループに陥る
        pin_num = 0
        fault_sentence = ''
        for i_p, o_p in zip(input_pattern, output_pattern):
            if i_p != 'x' and o_p == 'x':
                if not pin_num in already_fault_stuck:
                    # stuck の 判定
                    if i_p == '1':
                        stuck = '0'
                    elif i_p == '0':
                        stuck = '1'
                    fault_sentence = 'add_faults ppo_ps_reg[' + str(len(input_pattern) - pin_num -1 ) + '] -stuck ' + stuck
                    already_fault_stuck.append(pin_num)
                    break
            pin_num += 1
        #fault_sentence = 'add_faults ppo_ps_reg[11] -stuck 1'
        print('fault :' + fault_sentence)

        # ループの終了
        if len(fault_sentence) == 0 :
            with open('../' + target + '.test_siaaa', 'a+') as f:
                f.write(str(pattern_num) + ' ' + input_pattern + '\n')
            print('pattern finish')
            return input_pattern
            break

        # Test Pattern の 生成
        settings = dict(nangate_db = '../../data/Nangate/nangate45nm.db',
                nangate_v  = '../../data/Nangate/nangate.v',
                name       = target,
                clock      = clock_judge(target),
                vg         = '../' + target + '_comb.vg',
                stil       = target + '_comb.stil',
                pi_constraints = pi_constraints,
                fault_sentence = fault_sentence
                )
        Synopsys.run(shell='tmax', script='../../template/GeneratePatternForCombination', context=settings)

        # 生成されたテストパターンの取得
        try:
            next_input_pattern = SortMinTransition.extract_pattern_comb(target + '_comb.stil')[0]['pi']
        except:
            print('パターンが見つかりませんでした')
            continue
        next_input_pattern = list(next_input_pattern)
        #next_input_pattern.reverse()
        next_input_pattern = ''.join(next_input_pattern)
        next_input_pattern = next_input_pattern[:len(pattern['test_si'])].replace('N', 'x')
        print('testpi:' + next_input_pattern)
        bit = 0
        # このまま作成したテストパターンを次のテストパターンとしてもいいが,constraintsで指定したところがドントケア担っている可能性がある
        # そのため,以下で入力と比較して,どんとケアを訂正する
        next_input_pattern = list(next_input_pattern)
        for n, p in zip(next_input_pattern, input_pattern):
            if p != 'x' and n != p:
                next_input_pattern[bit] = input_pattern[bit]
            bit += 1
        next_input_pattern = ''.join(next_input_pattern)
        input_pattern = next_input_pattern[:]

        print('result:' + input_pattern)
Example #10
0
        next_input_pattern = ''.join(next_input_pattern)
        next_input_pattern = next_input_pattern[:len(pattern['test_si'])].replace('N', 'x')
        print('testpi:' + next_input_pattern)
        bit = 0
        # このまま作成したテストパターンを次のテストパターンとしてもいいが,constraintsで指定したところがドントケア担っている可能性がある
        # そのため,以下で入力と比較して,どんとケアを訂正する
        next_input_pattern = list(next_input_pattern)
        for n, p in zip(next_input_pattern, input_pattern):
            if p != 'x' and n != p:
                next_input_pattern[bit] = input_pattern[bit]
            bit += 1
        next_input_pattern = ''.join(next_input_pattern)
        input_pattern = next_input_pattern[:]

        print('result:' + input_pattern)



if __name__ == '__main__':
    target = '../b05'
    # vgファイルから組み合わせ回路を抜き出し,vgファイルに戻す
    Verilog.convert_verilog_to_json(target + '.vg', output_f= target + '.json')
    Verilog.extract_comb_circuit_from_verilog_json(target + '.json', target + '.json')
    Verilog.convert_json_to_verilog(target + '.json', output_f=target + '_comb.vg')

    num = sys.argv[1]
    # scan_inの抽出
    pattern = SortMinTransition.extract_pattern(target + '.stil')

    get_pattern(num, pattern[int(num)])