def nt_recv_filter_mac_top_test(dut): """Test bench main function.""" # start the clock cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ)) # no software reset dut.rst_sw <= 0 # reset the dut yield rstn(dut.clk, dut.rstn) # create, connect and reset AXI4-Lite writer axi_lite_writer = AXI_Lite_Writer() axi_lite_writer.connect(dut, dut.clk, AXI_CTRL_BIT_WIDTH, "ctrl") yield axi_lite_writer.rst() # create and reset AXI4-Stream writer axis_writer = AXIS_Writer() axis_writer.connect(dut, dut.clk, AXIS_BIT_WIDTH) yield axis_writer.rst() # create and reset AXI4-Stream reader axis_reader = AXIS_Reader() axis_reader.connect(dut, dut.clk, AXIS_BIT_WIDTH) yield axis_reader.rst() # start random toggling of axi stream reader tready cocotb.fork(toggle_signal(dut.clk, dut.m_axis_tready)) # perform a set of test. each run will generate its own random mac # addresses for i in range(N_RUNS): print("Test %d/%d" % (i + 1, N_RUNS)) yield perform_test(dut, axi_lite_writer, axis_writer, axis_reader)
def nt_recv_interpackettime_test(dut): """Test bench main function.""" # start the clock cocotb.fork(clk_gen(dut.clk156, CLK_FREQ_MHZ)) # no software reset dut.rst_sw156 <= 0 # reset the DuT yield rstn(dut.clk156, dut.rstn156) # create an AXI4-Stream reader, connect and reset it axis_reader = AXIS_Reader() axis_reader.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_reader.rst() # create an AXI4-Stream writer, connect and reset it axis_writer = AXIS_Writer() axis_writer.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_writer.rst() # generate some random packets pkts = [] for _ in range(N_PACKETS): pkts.append(gen_packet()) # start random toggling of AXI4-Stream reader TREADY cocotb.fork(toggle_signal(dut.clk156, dut.m_axis_tready)) # start one coroutine to apply packets on DuT input cocotb.fork(packets_write(dut, axis_writer, pkts)) # start one coroutine to read packets on DuT output coroutine_read = cocotb.fork(packets_read(dut, axis_reader, pkts)) # start one coroutine that monitors inter-packet times cocotb.fork(monitor_inter_packet_time(dut)) # wait for coroutines to complete yield coroutine_read.join()
def perform_test(dut, axis_writer, axis_reader, pkts): """Perform a test run.""" # create empty list of timestamp values timestamps = [] # start one coroutine to evaluate packets on dut output coroutine_recv = cocotb.fork( packets_read(dut, axis_reader, pkts, timestamps)) # start random toggling of axi stream reader tready signal cocotb.fork(toggle_signal(dut.clk156, dut.m_axis_tready)) # start monitoring of timestamp values cocotb.fork(monitor_timestamps(dut, pkts, timestamps)) yield RisingEdge(dut.clk156) # start one coroutine to apply packets on dut input cocotb.fork(packets_write(dut, axis_writer, pkts)) # wait until all packets have been received yield coroutine_recv.join()
def nt_gen_replay_top_test(dut): """Test bench main function.""" # start the clock cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ)) # no software reset dut.rst_sw <= 0 # reset dut yield rstn(dut.clk, dut.rstn) # open trace file trace = File("files/random.file") # get trace file size trace_size = trace.size() # trace file must be a multiple of the AXI data width if trace.size() % (AXI_MEM_BIT_WIDTH / 8) != 0: raise cocotb.result.TestFailure("invalid trace size") # calculate ring buffer sizes ring_buff_sizes = [] for ring_buff_size in RING_BUFF_SIZES: # size of ring buffer is determined by multiplying the size factor by # the size of the trace ring_buff_size = int(ring_buff_size * trace_size) # make sure that the ring buffer size is multiple of AXI data width if ring_buff_size % (AXI_MEM_BIT_WIDTH / 8) != 0: ring_buff_size += AXI_MEM_BIT_WIDTH/8 - \ ring_buff_size % (AXI_MEM_BIT_WIDTH/8) ring_buff_sizes.append(ring_buff_size) # create a ring buffer memory (initially of size 0) and connect it to the # DUT ring_buff = Mem(0) ring_buff.connect(dut, "ddr3") # create axi lite writer, connect and reset axi_lite_writer = AXI_Lite_Writer() axi_lite_writer.connect(dut, dut.clk, AXI_LITE_BIT_WIDTH, "ctrl") yield axi_lite_writer.rst() # create axi lite reader, connect and reset axi_lite_reader = AXI_Lite_Reader() axi_lite_reader.connect(dut, dut.clk, AXI_LITE_BIT_WIDTH, "ctrl") yield axi_lite_reader.rst() # create axi stream reader, connect and reset axis_reader = AXIS_Reader() axis_reader.connect(dut, dut.clk, AXIS_BIT_WIDTH) yield axis_reader.rst() # start the ring buffer memory main routine cocotb.fork(ring_buff.main()) # toggle m_axis_tready cocotb.fork(toggle_signal(dut.clk, dut.m_axis_tready)) # iterate over all ring buffer sizes for i, ring_buff_size in enumerate(ring_buff_sizes): # set ring buffer size ring_buff.set_size(ring_buff_size) # iterate over all addresses where ring buffer shall be located in # memory for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS): # print status print("Test %d/%d" % (i * len(RING_BUFF_ADDRS) + j + 1, len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES))) print("Ring Buff Addr: 0x%x, Size: %d" % (ring_buff_addr, ring_buff_size)) # we have a total of 8 GByte of memory. Make sure the ring buffer # fits at the desired address if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF: raise cocotb.result.TestFailure("ring buffer is too large") # to reduce the simulation memory footprint, provide the memory # module the first memory address that we acutally care about ring_buff.set_offset(ring_buff_addr) # configure ring buffer memory location yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_HI, ring_buff_addr >> 32) yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_LO, ring_buff_addr & 0xFFFFFFFF) # configure ring buffer address range yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_RANGE, ring_buff_size - 1) # configure trace size yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_TRACE_SIZE_HI, trace_size >> 32) yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_TRACE_SIZE_LO, trace_size & 0xFFFFFFFF) # reset write address pointer yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_ADDR_WR, 0x0) # make sure module initially is inactive status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) if status & 0x3 != 0: raise cocotb.reset.TestFailure("module is active") # start the module yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_START, 0x1) # wait a few cycles yield wait_n_cycles(dut.clk, 10) # start writing the ring buffer cocotb.fork( ring_buff_write(dut, ring_buff, trace, ring_buff_addr, axi_lite_reader, axi_lite_writer)) # start coroutine that checks dut output coroutine_chk_out = cocotb.fork( check_output(dut, trace, axis_reader)) # wait a few cycles and make sure module is active yield wait_n_cycles(dut.clk, 10) status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) if status & 0x1 == 0x0: raise cocotb.result.TestFailure("mem read not active") if status & 0x2 == 0x0: raise cocotb.result.TestFailure("packet assembly not active") # wait for output check to complete yield coroutine_chk_out.join() # wait a few cycles yield wait_n_cycles(dut.clk, 10) # make sure module is now inactive status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) if status & 0x3 != 0x0: raise cocotb.result.TestFailure("module does not become " + "inactive") # clear the ring buffer contents ring_buff.clear() # close the trace file trace.close()
def nt_recv_latency_test(dut): """Test bench main function.""" # start the clock cocotb.fork(clk_gen(dut.clk156, CLK_FREQ_MHZ)) # no software reset dut.rst_sw156 <= 0 # reset the dut yield rstn(dut.clk156, dut.rstn156) # create an AXI4-Stream reader, connect and reset it axis_reader = AXIS_Reader() axis_reader.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_reader.rst() # create an AXI4-Stream writer, connect and reset it axis_writer = AXIS_Writer() axis_writer.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_writer.rst() # start random toggling of AXI4-Stream reader TREADY cocotb.fork(toggle_signal(dut.clk156, dut.m_axis_tready)) # set current timestamp to be static at 8421376 dut.timestamp_i <= 8421376 yield RisingEdge(dut.clk156) # generate 70% of N_PACKETS IP packets and insert random timestamp in # packet header n_packets_ip = int(0.7 * N_PACKETS) pkts = [] timestamps = [] for _ in range(n_packets_ip): pkt = gen_packet() packet_insert_random_timestamp_header(pkt, timestamps) pkts.append(pkt) # then generate 30% of N_PACKETS non-IP packets. no timestamp will be # inserted for _ in range(N_PACKETS - n_packets_ip): pkt = gen_packet(eth_only=True) pkts.append(pkt) timestamps.append(None) # shuffle pkt and timestamp lists (in same order) tmp = list(zip(pkts, timestamps)) shuffle(tmp) pkts, timestamps = zip(*tmp) # we inserted timestamps in packet header dut.mode_i <= MODE_HEADER print("Test Timestamp Header") yield perform_test(dut, axis_writer, axis_reader, pkts, timestamps) # perform another test where timestamping is disabled dut.mode_i <= MODE_DISABLED print("Test Timestamp Disabled") yield perform_test(dut, axis_writer, axis_reader, pkts, timestamps) # next run some random tests with timestamp inserted at fixed byte position for i in range(N_REPEATS): # fixed byte position dut.mode_i <= MODE_FIXED_POS # randomly choose 16 bit or 24 bit timestamp width width = randint(0, 1) # find valid timestamp positions while True: pos = randint(0, 1518) if width == 0 and (pos % 8) < 7: break elif width == 1 and (pos % 8) < 6: break # set timestamp position and width dut.pos_i <= pos dut.width_i <= width # generate some ip packets and insert random timestamps pkts = [] timestamps = [] for _ in range(N_PACKETS): pkt = gen_packet() pkt = packet_insert_random_timestamp_fixed(pkt, timestamps, pos, width) pkts.append(pkt) # perform the test print("Test Timestamp Fixed Pos %d/%d (Pos: %d, Width: %d)" % (i + 1, N_REPEATS, pos, width)) yield perform_test(dut, axis_writer, axis_reader, pkts, timestamps)
def nt_gen_rate_ctrl_top_test(dut): """Test bench main function.""" # initially module is inactive dut.active_i <= 0 # no software reset dut.rst_sw156 <= 0 # start the clock cocotb.fork(clk_gen(dut.clk156, CLK_FREQ_MHZ)) # reset the DuT yield rstn(dut.clk156, dut.rstn156) # create AXI4-Stream writer and reader axis_writer = AXIS_Writer() axis_writer.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_writer.rst() axis_reader = AXIS_Reader() axis_reader.connect(dut, dut.clk156, AXIS_BIT_WIDTH) yield axis_reader.rst() # create AXI4-Lite writer and connect to DuT axi_lite_writer = AXI_Lite_Writer() axi_lite_writer.connect(dut, dut.clk156, AXI_CTRL_BIT_WIDTH, "ctrl") yield axi_lite_writer.rst() # create AXI4-Lite reader and connect to DuT axi_lite_reader = AXI_Lite_Reader() axi_lite_reader.connect(dut, dut.clk156, AXI_CTRL_BIT_WIDTH, "ctrl") yield axi_lite_reader.rst() # initially we are always ready to receive dut.m_axis_tready <= 1 # start a coroutine that counts the number of cycles between two packets # on the output axi stream cocotb.fork(count_cycles_between_axis_transmission(dut)) print("Test 1/4") # generate some packets and inter-packet times. we start with a constant # inter-packet time of 200 cycles, more than enough to transmit each packet pkts = [] for _ in range(N_PACKETS): pkts.append((gen_packet(), 200)) # write packet data cocotb.fork(packets_write(dut, axis_writer, pkts)) # wait a little yield wait_n_cycles(dut.clk156, 500) # start the module dut.active_i <= 1 # start coroutine that checks output and wait until it completes yield cocotb.fork(packets_read(dut, axis_reader, pkts, True)) # deactive the module dut.active_i <= 0 # make sure no warning was flagged status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) assert status == 0x0 print("Test 2/4") # now generate packets of fixed size of 800 bytes. Since the datapath is # 8 byte wide, it will take exactly 100 cycles to send them. Also select # a fixed inter-packet time of 100 cycles. packets should be sent # back-to-back pkts = [] for _ in range(N_PACKETS): pkt = Ether(src="53:00:00:00:00:01", dst="53:00:00:00:00:02") pkt /= ''.join( chr(random.randint(0, 255)) for _ in range(800 - len(pkt))) pkts.append((pkt, 100)) # apply packet data cocotb.fork(packets_write(dut, axis_writer, pkts)) # wait a little yield wait_n_cycles(dut.clk156, 1000) # start the module dut.active_i <= 1 # start coroutine that checks output and wait until it completes yield cocotb.fork(packets_read(dut, axis_reader, pkts, True)) # deactive the module dut.active_i <= 0 # make sure no warning was flagged status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) assert status == 0x0 print("Test 3/4") # repeat the experiment, but decrement inter-packet time to 99 cycles. # since inter-packet time is smaller than the packet transmit time, we # should get a warning pkts = [] for _ in range(N_PACKETS): pkt = Ether(src="53:00:00:00:00:01", dst="53:00:00:00:00:02") pkt /= ''.join( chr(random.randint(0, 255)) for _ in range(800 - len(pkt))) pkts.append((pkt, 99)) # apply packet data cocotb.fork(packets_write(dut, axis_writer, pkts)) # wait a little yield wait_n_cycles(dut.clk156, 500) # start the module dut.active_i <= 1 # start coroutine that checks output and wait until it completes yield cocotb.fork(packets_read(dut, axis_reader, pkts, False)) # deactive the module dut.active_i <= 0 # make sure a warning was flagged status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) assert status == 0x1 # perform software reset to clear warning flag yield axi_lite_writer.write(CPUREG_OFFSET_RST, 0x1) # now start toggeling tready cocotb.fork(toggle_signal(dut.clk156, dut.m_axis_tready)) print("Test 4/4") # repeat the experiment, inter-packet time back at 100 cycles. since the # slave is not always ready to receive, this should cause a warning pkts = [] for _ in range(N_PACKETS): pkt = Ether(src="53:00:00:00:00:01", dst="53:00:00:00:00:02") pkt /= ''.join( chr(random.randint(0, 255)) for _ in range(800 - len(pkt))) pkts.append((pkt, 100)) # apply packet data cocotb.fork(packets_write(dut, axis_writer, pkts)) # wait a little yield wait_n_cycles(dut.clk156, 500) # start the module dut.active_i <= 1 # start coroutine that checks output and wait until it completes yield cocotb.fork(packets_read(dut, axis_reader, pkts, False)) # deactive the module dut.active_i <= 0 # make sure no warning was flagged status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS) assert status == 0x1
def nt_gen_replay_mem_read_test(dut): """Test bench main function.""" # open trace file trace = File("files/random.file") # get trace file size trace_size = trace.size() # trace file size must be a multiple of AXI data width if trace.size() % (AXI_BIT_WIDTH / 8) != 0: raise cocotb.result.TestFailure("invalid trace size") # calculate ring buffer sizes ring_buff_sizes = [] for ring_buff_size in RING_BUFF_SIZES: # size of ring buffer is determined by multiplying the size factor by # the size of the trace ring_buff_size = int(ring_buff_size * trace_size) # make sure that the ring buffer size is multiple of AXI data width if ring_buff_size % (AXI_BIT_WIDTH / 8) != 0: ring_buff_size += AXI_BIT_WIDTH/8 - ring_buff_size % \ (AXI_BIT_WIDTH/8) ring_buff_sizes.append(ring_buff_size) # create a ring buffer memory (initially of size 0) and connect it to the # DUT ring_buff = Mem(0) ring_buff.connect(dut) # start the clock cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ)) # deassert sw reset dut.rst_sw <= 0 # initially module start is not triggered dut.ctrl_start_i <= 0 # reset dut yield rstn(dut.clk, dut.rstn) # start the ring buffer memory main routine cocotb.fork(ring_buff.main()) # wait some more clock cycles yield wait_n_cycles(dut.clk, 5) # randomly toggle fifo_prog_full input signal dut.fifo_prog_full_i <= 0 cocotb.fork(toggle_signal(dut.clk, dut.fifo_prog_full_i)) # iterate over all ring buffer sizes for i, ring_buff_size in enumerate(ring_buff_sizes): # set ring buffer size ring_buff.set_size(ring_buff_size) # iterate over all adderesses where ring buffer shall be located in # memory for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS): # print status print("Test %d/%d" % (i * len(RING_BUFF_ADDRS) + j + 1, len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES))) # we have a total of 8 GByte of memory. Make sure the ring buffer # fits at the desired address if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF: raise cocotb.result.TestFailure("ring buffer is too large") # to reduce the simulation memory footprint, provide the memory # module the first memory address that we actually care about ring_buff.set_offset(ring_buff_addr) # apply ring buffer memory location to dut dut.ctrl_mem_addr_hi_i <= ring_buff_addr >> 32 dut.ctrl_mem_addr_lo_i <= ring_buff_addr & 0xFFFFFFFF # apply ring buffer address range to dut dut.ctrl_mem_range_i <= ring_buff_size - 1 # apply trace size to dut dut.ctrl_trace_size_hi_i <= trace_size >> 32 dut.ctrl_trace_size_lo_i <= trace_size & 0xFFFFFFFF # reset write address pointer dut.ctrl_addr_wr_i <= 0 # start reading from the ring buffer dut.ctrl_start_i <= 1 yield RisingEdge(dut.clk) dut.ctrl_start_i <= 0 yield RisingEdge(dut.clk) # start writing the ring buffer cocotb.fork(ring_buff_write(dut, ring_buff, trace)) # start checking dut output and wait until it completes yield cocotb.fork(check_output(dut, trace)).join() # clear the ring buffer contents ring_buff.clear() # close trace file trace.close()