def assert_o_address(value, error_msg):
"""Check the output address"""
assertions.assertEqual(dut.o_address.value.binstr, value, error_msg)
def assert_control(control_bits, error_msg='wrong bits'):
"""Check the control bits output"""
# Reverse the order of the bits, so they have the same index as in verilog:
control_bits = control_bits[::-1]
# Remove blanks used for debug delimiter:
control_bits = control_bits.replace('_','')
# Check it:
assertions.assertEqual(dut.o_halt.value.binstr, control_bits[15], 'incorrect halt value')
assertions.assertEqual(dut.o_memory_address_in.value.binstr, control_bits[14], 'incorrect MAR In')
assertions.assertEqual(dut.o_ram_in.value.binstr, control_bits[13], 'incorrect RAM In')
assertions.assertEqual(dut.o_ram_out.value.binstr, control_bits[12], 'incorrect RAM Out')
assertions.assertEqual(dut.o_instruction_in.value.binstr, control_bits[11], 'incorrect Instruction In')
assertions.assertEqual(dut.o_instruction_out.value.binstr, control_bits[10], 'incorrect Instruction Out')
assertions.assertEqual(dut.o_register_a_in.value.binstr, control_bits[9], 'incorrect Register A In')
assertions.assertEqual(dut.o_register_a_out.value.binstr, control_bits[8], 'incorrect Register A Out')
assertions.assertEqual(dut.o_alu_out.value.binstr, control_bits[7], 'incorrect ALU Out')
assertions.assertEqual(dut.o_alu_subtract.value.binstr, control_bits[6], 'incorrect ALU Subtract')
assertions.assertEqual(dut.o_register_b_in.value.binstr, control_bits[5], 'incorrect Register B In')
assertions.assertEqual(dut.o_register_output_in.value.binstr, control_bits[4], 'incorrect Register Out In')
assertions.assertEqual(dut.o_program_counter_increment.value.binstr, control_bits[3], 'incorrect PC Increment')
assertions.assertEqual(dut.o_program_counter_out.value.binstr, control_bits[2], 'incorrect PC Out')
assertions.assertEqual(dut.o_program_counter_jump.value.binstr, control_bits[1], 'incorrect PC Jump')
assertions.assertEqual(dut.o_register_flags_in.value.binstr, control_bits[0], 'incorrect Register Flags In')
def assert_o_display(value, error_msg='Unexpected display value'):
"""Check the display out value"""
assertions.assertEqual(dut.o_display.value.binstr, value, error_msg)
def assert_o_bus(value, error_msg='wrong data'):
"""Check the bus out value"""
assertions.assertEqual(dut.o_bus.value.binstr, value, error_msg)
def assert_step(value, error_msg='wrong assumed step count'):
if isinstance(value, numbers.Number):
value = format(value, '03b')
assertions.assertEqual(dut.o_step.value.binstr, value, error_msg)
def assert_zero(zero=True, error_msg='expected zero flag did not register'):
"""Ensure that the zero flag was set (or not)"""
assertions.assertEqual(dut.o_flag_zero.value.binstr, '1' if zero else '0', error_msg)
def assert_o_unbuffered(value, error_msg='wrong data'):
"""Check the unbuffered output"""
assertions.assertEqual(dut.o_unbuffered.value.binstr, value, error_msg)
def assert_overflow(overflow=True, error_msg='expected overflow flag did not register'):
"""Ensure that the overflow flag was set (or not)"""
assertions.assertEqual(dut.o_flag_overflow.value.binstr, '1' if overflow else '0', error_msg)
def assert_o_count(value, error_msg):
"""Check the value of the output count"""
assertions.assertEqual(dut.o_count.value.binstr, value, error_msg)
def assert_io_data(value, error_msg):
"""Check the value of the data lines"""
if (isinstance(value, numbers.Number)):
assertions.assertEqual(dut.io_data.value, value, error_msg)
else:
assertions.assertEqual(dut.io_data.value.binstr, value, error_msg)
def assert_o_opcode(value, error_msg='wrong opcode'):
"""Check the decoded opcode output"""
assertions.assertEqual(dut.o_opcode.value.binstr, value, error_msg)
def assert_o_address(value, error_msg='wrong address'):
"""Check the decoded address output"""
assertions.assertEqual(dut.o_address.value.binstr, value, error_msg)