def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = K4B2G1646F(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self, platform, csr_data_width=8, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
csr_data_width=csr_data_width,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
bios_size = 0x8000
# sdram
sdram_module = K4B2G1646F(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self,
sys_clk_freq=int(100e6),
integrated_rom_size=0x8000,
**kwargs):
platform = netv2.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self,
variant="a7-35",
sys_clk_freq=int(100e6),
with_pcie=False,
with_ethernet=False,
**kwargs):
platform = netv2.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on NeTV2",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=K4B2G1646F(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_spi_xip=False,
**kwargs):
platform = netv2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=K4B2G1646F(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPI XIP ----------------------------------------------------------------------------------
if with_spi_xip:
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
spi_xip_size = 1024 * 1024 * 8
self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
self.submodules.spictl = LiteSPI(phy=self.spiphy,
endianness=self.cpu.endianness)
spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None),
size=spi_xip_size,
cached=False)
self.bus.add_slave(name="spixip",
slave=self.spictl.bus,
region=spi_xip_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
platform = netv2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, platform, csr_data_width=8, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
csr_data_width=csr_data_width,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
# sdram
sdram_module = K4B2G1646F(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_gtp=True,
gtp_connector="pcie",
gtp_refclk="pcie",
gtp_linerate=5e9,
with_gtp_bist=True,
with_gtp_freqmeter=True,
with_record=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="PCIe Analyzer LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
if with_gtp:
assert gtp_refclk in ["pcie", "internal"]
if gtp_refclk == "pcie":
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
else:
refclk = Signal()
refclk_freq = 100e6
self.comb += refclk.eq(ClockSignal("clk100"))
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]"
)
# GTP PLL ----------------------------------------------------------------------------------
if with_gtp:
qpll = GTPQuadPLL(refclk, refclk_freq, gtp_linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
if with_gtp:
for i in range(2):
tx_pads = platform.request(gtp_connector + "_tx", i)
rx_pads = platform.request(gtp_connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
# GTPs FreqMeters --------------------------------------------------------------------------
if with_gtp_freqmeter:
self.submodules.gtp0_tx_freq = FreqMeter(ClockSignal("gtp0_tx"))
self.submodules.gtp0_rx_freq = FreqMeter(ClockSignal("gtp0_rx"))
self.submodules.gtp1_tx_freq = FreqMeter(ClockSignal("gtp1_tx"))
self.submodules.gtp1_rx_freq = FreqMeter(ClockSignal("gtp1_rx"))
self.add_csr("gtp0_tx_freq")
self.add_csr("gtp0_rx_freq")
self.add_csr("gtp1_tx_freq")
self.add_csr("gtp1_rx_freq")
# GTPs BIST --------------------------------------------------------------------------------
if with_gtp_bist:
self.submodules.gtp0_tx_bist = GTPTXBIST(self.gtp0, "gtp0_tx")
self.submodules.gtp0_rx_bist = GTPRXBIST(self.gtp0, "gtp0_rx")
self.submodules.gtp1_tx_bist = GTPTXBIST(self.gtp1, "gtp1_tx")
self.submodules.gtp1_rx_bist = GTPRXBIST(self.gtp1, "gtp1_rx")
self.add_csr("gtp0_tx_bist")
self.add_csr("gtp0_rx_bist")
self.add_csr("gtp1_tx_bist")
self.add_csr("gtp1_rx_bist")
# Record -----------------------------------------------------------------------------------
# FIXME: use better data/ctrl packing (or separate recorders)
if with_record:
# Convert RX stream from 16-bit@250MHz to 64-bit@sys_clk
rx_converter = stream.StrideConverter([("data", 16), ("ctrl", 2)],
[("data", 96), ("ctrl", 12)],
reverse=False)
rx_converter = ClockDomainsRenamer("gtp0_rx")(rx_converter)
self.submodules.rx_converter = rx_converter
rx_cdc = stream.AsyncFIFO([("data", 96), ("ctrl", 12)],
8,
buffered=True)
rx_cdc = ClockDomainsRenamer({
"write": "gtp0_rx",
"read": "sys"
})(rx_cdc)
self.submodules.rx_cdc = rx_cdc
# RX DMA Recorder
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 128))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.comb += [
gtp.source.connect(rx_converter.sink),
rx_converter.source.connect(rx_cdc.sink),
self.rx_dma_recorder.sink.valid.eq(rx_cdc.source.valid),
self.rx_dma_recorder.sink.data[0:96].eq(rx_cdc.source.data),
self.rx_dma_recorder.sink.data[96:108].eq(rx_cdc.source.ctrl),
]
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_pcie=True,
with_sdram_dmas=False,
with_hdmi_in0=True,
with_hdmi_out0=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
cpu_variant="lite",
l2_size=128,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="NeTV2 LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("icap")
# Flash ------------------------------------------------------------------------------------
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY ----------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=64,
bar0_size=0x20000)
platform.add_false_path_constraint(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint -----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge ----------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 ---------------------------------------------------------------------------------
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1 ---------------------------------------------------------------------------------
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI ----------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# FIXME : Dummy counter capture, connect to HDMI In ------------------------------------
pcie_dma0_counter = Signal(32)
self.sync += [
self.pcie_dma0.sink.valid.eq(1),
If(self.pcie_dma0.sink.ready,
pcie_dma0_counter.eq(pcie_dma0_counter + 1)),
self.pcie_dma0.sink.data.eq(pcie_dma0_counter)
]
pcie_dma1_counter = Signal(32)
self.sync += [
self.pcie_dma1.sink.valid.eq(1),
If(self.pcie_dma1.sink.ready,
pcie_dma1_counter.eq(pcie_dma1_counter + 2)),
self.pcie_dma1.sink.data.eq(pcie_dma1_counter)
]
# SDRAM DMAs -------------------------------------------------------------------------------
if with_sdram_dmas:
self.submodules.sdram_reader = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_reader.add_csr()
self.add_csr("sdram_reader")
self.submodules.sdram_writer = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_writer.add_csr()
self.add_csr("sdram_writer")
# HDMI In 0 --------------------------------------------------------------------------------
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
pads=hdmi_in0_pads,
dram_port=self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6)
# HDMI Out 0 -------------------------------------------------------------------------------
if with_hdmi_out0:
self.submodules.hdmi_out0 = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out", 0),
dram_port=self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=512)
self.add_csr("hdmi_out0")
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)