def __init__(self, platform, **kwargs):
clk_freq = 80 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash2x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
# sdram
sdram_module = AS4C16M16(self.clk_freq, "1:1")
self.submodules.ddrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
sys_clk_freq = 80 * 1000000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = AS4C16M16(sys_clk_freq, "1:1")
self.submodules.ddrphy = gensdrphy.GENSDRPHY(
platform.request("sdram"))
self.add_csr("ddrphy")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlash(
platform.request("spiflash2x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus,
platform.spiflash_total_size)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
