def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"):
BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32, l2_size=32)
# ethernet mac/udp/ip stack
self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=True)
# etherbone bridge
self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234))
self.add_wb_master(self.cpu_or_bridge.wishbone.bus)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model,
debug=False,
loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model,
mac_address,
ip_address,
debug=False)
self.submodules.ip_model = ip.IP(self.mac_model,
mac_address,
ip_address,
debug=False,
loopback=False)
self.submodules.udp_model = udp.UDP(self.ip_model,
ip_address,
debug=False,
loopback=False)
self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model,
debug=False)
self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address,
ip_address, 100000)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 0x1234)
self.submodules.sram = wishbone.SRAM(1024)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.etherbone.wishbone.bus, self.sram.bus)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get(
'cpu_type', 'lm32') != 'lm32':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# Ethernet Phy
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# Ethernet Core
etherbone_mac_address = 0x10e2d5000000
etherbone_ip_address = "192.168.100.50"
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=self.clk_freq)
# Etherbone Core
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 25e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs):
BaseSoc.__init__(self, **kwargs)
# ethernet PHY and UDP/IP stack
mac_address = 0x10e2d5001000
ip_address = "192.168.1.50"
self.submodules.ethphy = LiteEthPHY(
self.platform.request("eth_clocks"),
self.platform.request("eth"),
self.clk_freq,
# avoid huge reset delay in simulation
with_hw_init_reset="synth" in argv)
self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address,
convert_ip(ip_address),
self.clk_freq)
# MAC = wishbone slave = to let the CPU talk over ethernet
# self.submodules.ethmac = LiteEthMAC(
# phy=self.ethphy, dw=32, interface="wishbone",
# endianness="little", with_preamble_crc=False
# )
# self.add_wb_slave(
# mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus
# )
# self.add_memory_region(
# "ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000
# )
# Etherbone = wishbone master = read and write registers remotely
self.submodules.etherbone = LiteEthEtherbone(self.core.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# core
self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 25e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 25e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform):
BaseSoC.__init__(self,
platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50")
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
self.add_wb_master(self.etherbone.master.bus)
def __init__(self, eth_phy=0, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy),
tx_delay=0e-9, # 0ns FPGA delay (Clk delay added by PHY)
rx_delay=2e-9
) # 2ns FPGA delay to compensate Clk routing to IDDRX1F
self.add_csr("ethphy")
# core
self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32)
# Ethernet PHY and UDP/IP stack
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=True)
# Etherbone bridge
self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 20000))
self.add_wb_master(self.cpu_or_bridge.master.bus)
self.specials += [
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
cpu_type=None,
mac_address=0x10e2d5000000,
ip_address="192.168.100.50",
**kwargs):
clk_freq = int(142e6)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
integrated_main_ram_size=0x8000,
integrated_rom_size=0x10000,
integrated_sram_size=0x8000,
csr_data_width=32,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# ethernet mac/udp/ip stack
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=True)
self.add_csr("ethcore")
# etherbone bridge
self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234))
self.add_wb_master(self.cpu_or_bridge.wishbone.bus)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
period_ns(125e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
period_ns(125e6))
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
with_ethernet=True,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int(133e6)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Daisho USB3.0 Test Design",
with_timer=False)
self.submodules.crg = _CRG(platform)
# uart <--> wishbone
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 7.5)
# ethernet PHY and UDP/IP stack
if with_ethernet:
self.submodules.eth_phy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.eth_core = LiteEthUDPIPCore(
self.eth_phy, mac_address, convert_ip(ip_address), clk_freq)
# ethernet <--> wishbone
self.submodules.etherbone = LiteEthEtherbone(
self.eth_core.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
8.0)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self,
platform,
mac_address=0x10e2d5000004,
ip_address="10.0.11.2"):
BaseSoC.__init__(self,
platform,
cpu_type="vexriscv",
cpu_variant="debug",
csr_data_width=8,
l2_size=32)
# ethernet mac/udp/ip stack
self.submodules.ethphy = LiteEthPHYMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=True)
# vexriscv debugging, at offset 0xf00f0000
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu_or_bridge.debug_bus, 0x10)
# Hook Etherbone up to the Wishbone bus, providing Wishbone over Ethernet.
etherbone_cd = ClockDomain("etherbone")
self.clock_domains += etherbone_cd
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
1234,
mode="master",
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
period_ns(25e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
period_ns(25e6))
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs):
HelloLtc.__init__(self, **kwargs)
p = self.platform
# ethernet PHY and UDP/IP stack
mac_address = 0x01E625688D7C
ip_address = "192.168.1.50"
self.submodules.ethphy = LiteEthPHY(
p.request("eth_clocks"),
p.request("eth"),
self.clk_freq,
# avoid huge reset delay in simulation
with_hw_init_reset="synth" in argv
)
self.submodules.core = LiteEthUDPIPCore(
self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq
)
# Etherbone = wishbone master = read and write registers remotely
self.submodules.etherbone = LiteEthEtherbone(
self.core.udp, 1234, mode="master"
)
self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self,
platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.42",
**kwargs):
BaseSoC.__init__(self, platform, **kwargs)
# Ethernet PHY and UDP/IP stack
self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address,
convert_ip(ip_address),
self.clk_freq,
with_icmp=False)
# Etherbone bridge
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 20000)
self.add_wb_master(self.etherbone.master.bus)
self.specials += [
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk)
]
platform.add_platform_command(
"""
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
NET "{eth_clocks_rx}" TNM_NET = "GRPeth_clocks_rx";
NET "{eth_rx_clk}" TNM_NET = "GRPeth_rx_clk";
NET "{eth_tx_clk}" TNM_NET = "GRPeth_tx_clk";
TIMESPEC "TSise_sucks1" = FROM "GRPeth_clocks_rx" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPeth_clocks_rx" TIG;
TIMESPEC "TSise_sucks3" = FROM "GRPeth_tx_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks4" = FROM "GRPsys_clk" TO "GRPeth_tx_clk" TIG;
TIMESPEC "TSise_sucks5" = FROM "GRPeth_rx_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks6" = FROM "GRPsys_clk" TO "GRPeth_rx_clk" TIG;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_rx_clk=self.ethphy.crg.cd_eth_rx.clk,
eth_tx_clk=self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int(1e9/platform.default_clk_period)
SoCMini.__init__(self, platform, clk_freq, ident="Daisho USB3.0 Test Design", ident_version=True)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# uart <--> wishbone
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# ethernet PHY and UDP/IP stack
self.submodules.eth_phy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
clk_freq=clk_freq)
self.submodules.eth_core = LiteEthUDPIPCore(self.eth_phy,
mac_address,
convert_ip(ip_address),
clk_freq)
# ethernet <--> wishbone
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 6.0)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False,
etherbone_mac_address=0x10e2d5000000,
etherbone_ip_address="192.168.1.50",
with_analyzer=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation",
ident_version=True,
with_uart=False,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# Serial -----------------------------------------------------------------------------------
self.submodules.uart_phy = uart.RS232PHYModel(
platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart")
self.add_interrupt("uart")
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings
phy_settings = PhySettings(memtype="SDR",
databits=32,
dfi_databits=16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
assert not (with_ethernet and with_etherbone
) # FIXME: fix simulator with 2 ethernet interfaces
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({
"eth_tx": "ethphy_eth_tx",
"eth_rx": "ethphy_eth_rx"
})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Ethernet ---------------------------------------------------------------------------------
if with_etherbone:
# Ethernet PHY
self.submodules.etherbonephy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("etherbonephy")
# Ethernet MAC
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=sys_clk_freq)
self.submodules.etherbonecore = etherbonecore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.etherbonecore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.add_csr("analyzer")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = SimPlatform("SIM", _io)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
def add_xram(self, name, origin, mem, mode='rw'):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram = wishbone.SRAM(mem,
bus=wishbone.Interface(data_width=mem.width),
read_only='w' not in mode)
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(ram_bus, ram.bus)
region = SoCRegion(origin=origin,
size=mem.width // 8 * mem.depth,
mode=mode)
self.bus.add_slave(name, ram_bus, region)
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
# ------------------------------ writer ------------------------------------
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port)
self.add_csr('writer')
# TODO: Rename as 'pattern_wr_w?'
add_xram(self,
name='pattern_w0',
mem=self.writer.memory_w0,
origin=0x20000000)
add_xram(self,
name='pattern_w1',
mem=self.writer.memory_w1,
origin=0x21000000)
add_xram(self,
name='pattern_w2',
mem=self.writer.memory_w2,
origin=0x22000000)
add_xram(self,
name='pattern_w3',
mem=self.writer.memory_w3,
origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=self.writer.memory_adr,
origin=0x24000000)
# ----------------------------- reader -------------------------------------
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port)
self.add_csr('reader')
add_xram(self,
name='pattern_rd_w0',
mem=self.reader.memory_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=self.reader.memory_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=self.reader.memory_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=self.reader.memory_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=self.reader.memory_adr,
origin=0x34000000)
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
scratchpad_size = 2**10
payload_mem = Memory(32, 2**10)
scratchpad_mem = Memory(scratchpad_width,
scratchpad_size // (scratchpad_width // 8))
self.specials += payload_mem, scratchpad_mem
add_xram(self, name='payload', mem=payload_mem, origin=0x35000000)
add_xram(self,
name='scratchpad',
mem=scratchpad_mem,
origin=0x36000000,
mode='r')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi=self.sdram.dfii.ext_dfi,
dfi_sel=self.sdram.dfii.ext_dfi_sel,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_gtp=True,
gtp_connector="pcie",
gtp_refclk="pcie",
gtp_linerate=5e9,
with_gtp_bist=True,
with_gtp_freqmeter=True,
with_record=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="PCIe Analyzer LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
if with_gtp:
assert gtp_refclk in ["pcie", "internal"]
if gtp_refclk == "pcie":
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
else:
refclk = Signal()
refclk_freq = 100e6
self.comb += refclk.eq(ClockSignal("clk100"))
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]"
)
# GTP PLL ----------------------------------------------------------------------------------
if with_gtp:
qpll = GTPQuadPLL(refclk, refclk_freq, gtp_linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
if with_gtp:
for i in range(2):
tx_pads = platform.request(gtp_connector + "_tx", i)
rx_pads = platform.request(gtp_connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
# GTPs FreqMeters --------------------------------------------------------------------------
if with_gtp_freqmeter:
self.submodules.gtp0_tx_freq = FreqMeter(ClockSignal("gtp0_tx"))
self.submodules.gtp0_rx_freq = FreqMeter(ClockSignal("gtp0_rx"))
self.submodules.gtp1_tx_freq = FreqMeter(ClockSignal("gtp1_tx"))
self.submodules.gtp1_rx_freq = FreqMeter(ClockSignal("gtp1_rx"))
self.add_csr("gtp0_tx_freq")
self.add_csr("gtp0_rx_freq")
self.add_csr("gtp1_tx_freq")
self.add_csr("gtp1_rx_freq")
# GTPs BIST --------------------------------------------------------------------------------
if with_gtp_bist:
self.submodules.gtp0_tx_bist = GTPTXBIST(self.gtp0, "gtp0_tx")
self.submodules.gtp0_rx_bist = GTPRXBIST(self.gtp0, "gtp0_rx")
self.submodules.gtp1_tx_bist = GTPTXBIST(self.gtp1, "gtp1_tx")
self.submodules.gtp1_rx_bist = GTPRXBIST(self.gtp1, "gtp1_rx")
self.add_csr("gtp0_tx_bist")
self.add_csr("gtp0_rx_bist")
self.add_csr("gtp1_tx_bist")
self.add_csr("gtp1_rx_bist")
# Record -----------------------------------------------------------------------------------
# FIXME: use better data/ctrl packing (or separate recorders)
if with_record:
# Convert RX stream from 16-bit@250MHz to 64-bit@sys_clk
rx_converter = stream.StrideConverter([("data", 16), ("ctrl", 2)],
[("data", 96), ("ctrl", 12)],
reverse=False)
rx_converter = ClockDomainsRenamer("gtp0_rx")(rx_converter)
self.submodules.rx_converter = rx_converter
rx_cdc = stream.AsyncFIFO([("data", 96), ("ctrl", 12)],
8,
buffered=True)
rx_cdc = ClockDomainsRenamer({
"write": "gtp0_rx",
"read": "sys"
})(rx_cdc)
self.submodules.rx_cdc = rx_cdc
# RX DMA Recorder
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 128))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.comb += [
gtp.source.connect(rx_converter.sink),
rx_converter.source.connect(rx_cdc.sink),
self.rx_dma_recorder.sink.valid.eq(rx_cdc.source.valid),
self.rx_dma_recorder.sink.data[0:96].eq(rx_cdc.source.data),
self.rx_dma_recorder.sink.data[96:108].eq(rx_cdc.source.ctrl),
]
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_pcie=True,
with_sdram_dmas=False,
with_hdmi_in0=True,
with_hdmi_out0=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
cpu_variant="lite",
l2_size=128,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="NeTV2 LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("icap")
# Flash ------------------------------------------------------------------------------------
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY ----------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=64,
bar0_size=0x20000)
platform.add_false_path_constraint(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint -----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge ----------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 ---------------------------------------------------------------------------------
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1 ---------------------------------------------------------------------------------
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI ----------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# FIXME : Dummy counter capture, connect to HDMI In ------------------------------------
pcie_dma0_counter = Signal(32)
self.sync += [
self.pcie_dma0.sink.valid.eq(1),
If(self.pcie_dma0.sink.ready,
pcie_dma0_counter.eq(pcie_dma0_counter + 1)),
self.pcie_dma0.sink.data.eq(pcie_dma0_counter)
]
pcie_dma1_counter = Signal(32)
self.sync += [
self.pcie_dma1.sink.valid.eq(1),
If(self.pcie_dma1.sink.ready,
pcie_dma1_counter.eq(pcie_dma1_counter + 2)),
self.pcie_dma1.sink.data.eq(pcie_dma1_counter)
]
# SDRAM DMAs -------------------------------------------------------------------------------
if with_sdram_dmas:
self.submodules.sdram_reader = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_reader.add_csr()
self.add_csr("sdram_reader")
self.submodules.sdram_writer = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_writer.add_csr()
self.add_csr("sdram_writer")
# HDMI In 0 --------------------------------------------------------------------------------
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
pads=hdmi_in0_pads,
dram_port=self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6)
# HDMI Out 0 -------------------------------------------------------------------------------
if with_hdmi_out0:
self.submodules.hdmi_out0 = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out", 0),
dram_port=self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=512)
self.add_csr("hdmi_out0")
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
def __init__(self, sdram_module, sdram_data_width, **kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,
integrated_rom_size = 0x8000,
integrated_sram_size = 0x1000,
uart_name = "crossover",
l2_size = 0,
csr_data_width = 32,
**kwargs
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDR SDRAM --------------------------------------------------------------------------------
from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module,
settings = phy_settings,
clk_freq = sdram_clk_freq)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Disable Memtest for simulation speedup
self.add_constant("MEMTEST_BUS_SIZE", 0)
self.add_constant("MEMTEST_ADDR_SIZE", 0)
self.add_constant("MEMTEST_DATA_SIZE", 0)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.add_csr("ethphy")
# core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50",
clk_freq = sys_clk_freq)
self.submodules.ethcore = ethcore
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Record -----------------------------------------------------------------------------------
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(self.sdram.crossbar.get_port("write", 32))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.submodules.tx_dma_recorder = LiteDRAMDMAWriter(self.sdram.crossbar.get_port("write", 32))
self.tx_dma_recorder.add_csr()
self.add_csr("tx_dma_recorder")
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.comb += [
self.rx_dma_recorder.sink.valid.eq(1),
self.rx_dma_recorder.sink.data.eq(counter),
self.tx_dma_recorder.sink.valid.eq(1),
self.tx_dma_recorder.sink.data.eq(counter),
]
def __init__(self,
sys_clk_freq=int(100e6),
with_etherbone=True,
eth_ip="192.168.1.50",
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Siglent SDS1104X-E",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_ethernet=with_etherbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac",
getattr(self.mem_map, "ethmac", None),
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
self.add_constant(
"ETH_PHY_NO_RESET"
) # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk,
1e9 / self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk,
1e9 / self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", {
"pix_clk": 33.3e6,
"h_active": 800,
"h_blanking": 256,
"h_sync_offset": 210,
"h_sync_width": 1,
"v_active": 480,
"v_blanking": 45,
"v_sync_offset": 22,
"v_sync_width": 1,
})
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("lcd"),
clock_domain="dvi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings=video_timings,
clock_domain="dvi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings=video_timings,
clock_domain="dvi")
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
pix_freq = 148.50e6
########## hdmi in 0 (raw tmds)
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in0 = hdmi_in0 = HDMIIn(hdmi_in0_pads,
device="xc7",
split_mmcm=True,
hdmi=True)
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk)
# don't add clock timings here, we add a root clock constraint that derives the rest automatically
# define path constraints individually to sysclk to avoid accidentally declaring other inter-clock paths as false paths
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix_o.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix5x_o.clk)
hdmi_out0_pads = platform.request("hdmi_out", 0)
self.submodules.hdmi_out0_clk_gen = S7HDMIOutEncoderSerializer(
hdmi_out0_pads.clk_p, hdmi_out0_pads.clk_n, bypass_encoder=True)
self.comb += self.hdmi_out0_clk_gen.data.eq(
Signal(10, reset=0b0000011111))
self.submodules.hdmi_out0_phy = S7HDMIOutPHY(hdmi_out0_pads,
mode="raw")
# hdmi over
self.comb += [
platform.request("hdmi_sda_over_up").eq(0),
platform.request("hdmi_sda_over_dn").eq(0),
]
platform.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_in_ibufds/ob]"
)
# extract timing info from HDMI input 0, and put it into a stream that we can pass later on as a genlock object
self.hdmi_in0_timing = hdmi_in0_timing = stream.Endpoint(
frame_timing_layout)
self.sync.pix_o += [
hdmi_in0_timing.de.eq(self.hdmi_in0.syncpol.de),
hdmi_in0_timing.hsync.eq(self.hdmi_in0.syncpol.hsync),
hdmi_in0_timing.vsync.eq(self.hdmi_in0.syncpol.vsync),
If(
self.hdmi_in0.syncpol.valid_o,
hdmi_in0_timing.valid.eq(1),
).Else(hdmi_in0_timing.valid.eq(0), )
]
early_line_end = Signal()
self.comb += early_line_end.eq(hdmi_in0_timing.de
& ~self.hdmi_in0.syncpol.de)
########## hdmi in 1
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=1024,
device="xc7",
split_mmcm=False,
mode="rgb",
hdmi=True)
self.comb += self.hdmi_in1_freq.clk.eq(
self.hdmi_in1.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in1.clocking.cd_pix5x.clk)
######## Constraints
# instantiate fundamental clocks -- Vivado will derive the rest via PLL programmings
self.platform.add_platform_command(
"create_clock -name clk50 -period 20.0 [get_nets clk50]")
self.platform.add_platform_command(
"create_clock -name hdmi_in0_clk_p -period 6.734006734006734 [get_nets hdmi_in0_clk_p]"
)
self.platform.add_platform_command(
"create_clock -name hdmi_in1_clk_p -period 6.734006734006734 [get_nets hdmi_in1_clk_p]"
)
# exclude all generated clocks from the fundamental HDMI cloks and sys clocks
self.platform.add_platform_command(
"set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in0_clk_p]] -asynchronous"
)
self.platform.add_platform_command(
"set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets hdmi_in1_clk_p]] -asynchronous"
)
# make sure derived clocks get named correctly; I think this is now being done right without these args
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix_clk [get_pins MMCME2_ADV/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix1p25x_clk [get_pins MMCME2_ADV/CLKOUT1]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in0_pix5x_clk [get_pins MMCME2_ADV/CLKOUT2]")
# self.platform.add_platform_command("create_generated_clock -name pix_o_clk [get_pins PLLE2_ADV/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name pix5x_o_clk [get_pins PLLE2_ADV/CLKOUT2]")
#
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix_clk [get_pins MMCME2_ADV_1/CLKOUT0]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix1p25x_clk [get_pins MMCME2_ADV_1/CLKOUT1]")
# self.platform.add_platform_command("create_generated_clock -name hdmi_in1_pix5x_clk [get_pins MMCME2_ADV_1/CLKOUT2]")
# don't time the high-fanout reset paths
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in1_pix_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in0_pix_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in1_pix1p25x_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets hdmi_in0_pix1p25x_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets pix_o_rst]")
self.platform.add_platform_command(
"set_false_path -through [get_nets soc_videooverlaysoc_hdmi_out0_clk_gen_ce]"
) # derived from reset
# gearbox timing is a multi-cycle path: FAST to SLOW synchronous clock domains
self.platform.add_platform_command(
"set_multicycle_path 2 -setup -start -from [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 1 -hold -from [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in0_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 2 -setup -start -from [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk0]"
)
self.platform.add_platform_command(
"set_multicycle_path 1 -hold -from [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk1] -to [get_clocks soc_videooverlaysoc_hdmi_in1_mmcm_clk0]"
)
############### hdmi out 1 (overlay rgb)
out_dram_port = self.sdram.crossbar.get_port(mode="read",
cd="pix_o",
dw=32,
reverse=True)
self.submodules.hdmi_core_out0 = VideoOutCore(
out_dram_port,
mode="rgb",
fifo_depth=1024,
genlock_stream=hdmi_in0_timing)
core_source_valid_d = Signal()
core_source_data_d = Signal(32)
sync_cd = getattr(self.sync, out_dram_port.cd)
sync_cd += [
core_source_valid_d.eq(self.hdmi_core_out0.source.valid),
core_source_data_d.eq(self.hdmi_core_out0.source.data),
]
####### timing stream extraction
timing_rgb_delay = TimingDelayRGB(
4
) # create the delay element with specified delay...note if you say TimingDelay() the code runs happily with no error, because Python doesn't typecheck
timing_rgb_delay = ClockDomainsRenamer("pix_o")(
timing_rgb_delay) # assign a clock domain to the delay element
self.submodules += timing_rgb_delay # DONT FORGET THIS LINE OR ELSE NOTHING HAPPENS....
self.hdmi_out0_rgb = hdmi_out0_rgb = stream.Endpoint(
rgb_layout) # instantiate the input record
self.hdmi_out0_rgb_d = hdmi_out0_rgb_d = stream.Endpoint(
rgb_layout) # instantiate the output record
self.comb += [
self.hdmi_core_out0.source.ready.eq(
1
), # don't forget to tell the upstream component that we're ready, or we get a monochrome screen...
hdmi_out0_rgb.b.eq(
core_source_data_d[0:8]
), # wire up the specific elements of the input record
hdmi_out0_rgb.g.eq(core_source_data_d[8:16]),
hdmi_out0_rgb.r.eq(core_source_data_d[16:24]),
hdmi_out0_rgb.valid.eq(
core_source_valid_d
), # not used, but hook it up anyways in case we need it later...
timing_rgb_delay.sink.eq(
hdmi_out0_rgb), # assign input stream to the delay element
hdmi_out0_rgb_d.eq(timing_rgb_delay.source
) # grab output stream from the delay element
# the output records are directly consumed down below
]
##### HDCP engine
platform.add_source(os.path.join("overlay", "i2c_snoop.v"))
platform.add_source(os.path.join("overlay", "diff_network.v"))
platform.add_source(os.path.join("overlay", "hdcp_block.v"))
platform.add_source(os.path.join("overlay", "hdcp_cipher.v"))
platform.add_source(os.path.join("overlay", "hdcp_lfsr.v"))
platform.add_source(os.path.join("overlay", "shuffle_network.v"))
platform.add_source(os.path.join("overlay", "hdcp_mod.v"))
self.submodules.i2c_snoop = i2c_snoop = I2Csnoop(hdmi_in0_pads)
self.submodules.hdcp = hdcp = HDCP(hdmi_in0_timing)
self.comb += hdcp.line_end.eq(
early_line_end
) # wire up an early line-end signal to meet rekey timing
Aksv14 = Signal()
Aksv14_r = Signal()
self.specials += MultiReg(i2c_snoop.Aksv14_write,
Aksv14,
odomain="pix_o")
self.sync.pix_o += [
Aksv14_r.eq(Aksv14),
hdcp.Aksv14_write.eq(
Aksv14 & ~Aksv14_r), # should be a rising-edge strobe only
# hdcp.hpd.eq(hdmi_in0.edid._hpd_notif.status),
hdcp.hdcp_ena.eq(hdmi_in0.decode_terc4.encrypting_video
| hdmi_in0.decode_terc4.encrypting_data),
hdcp.hpd.eq(hdmi_in0_pads.hpd_notif),
hdcp.An.eq(i2c_snoop.An),
hdcp.ctl_code.eq(hdmi_in0.decode_terc4.ctl_code),
]
self.comb += platform.request("hpd_en").eq(hdcp.hpd_ena.storage)
###### overlay pixel encoders
self.submodules.encoder_red = encoder_red = ClockDomainsRenamer(
"pix_o")(Encoder())
self.submodules.encoder_grn = encoder_grn = ClockDomainsRenamer(
"pix_o")(Encoder())
self.submodules.encoder_blu = encoder_blu = ClockDomainsRenamer(
"pix_o")(Encoder())
self.comb += [
If(
hdcp.Km_valid.
storage, # this is a proxy for HDCP being initialized
encoder_red.d.eq(hdmi_out0_rgb.r
^ hdcp.cipher_stream[16:]), # 23:16
encoder_grn.d.eq(hdmi_out0_rgb.g
^ hdcp.cipher_stream[8:16]), # 15:8
encoder_blu.d.eq(
(hdmi_out0_rgb.b ^ hdcp.cipher_stream[0:8])), # 7:0
# encoder_red.d.eq(hdcp.cipher_stream[16:]), # 23:16
# encoder_grn.d.eq(hdcp.cipher_stream[8:16]), # 15:8
# encoder_blu.d.eq(hdcp.cipher_stream[0:8]), # 7:0
).Else(
encoder_red.d.eq(hdmi_out0_rgb.r),
encoder_grn.d.eq(hdmi_out0_rgb.g),
encoder_blu.d.eq(hdmi_out0_rgb.b),
),
encoder_red.de.eq(1),
encoder_red.c.eq(
0
), # we promise to use this only during video areas, so "c" is always 0
encoder_grn.de.eq(1),
encoder_grn.c.eq(0),
encoder_blu.de.eq(1),
encoder_blu.c.eq(0),
]
# hdmi in to hdmi out
c0_pix_o = Signal(10)
c1_pix_o = Signal(10)
c2_pix_o = Signal(10)
c0 = Signal(10)
c1 = Signal(10)
c2 = Signal(10)
self.comb += [
c0.eq(self.hdmi_in0.syncpol.c0),
c1.eq(self.hdmi_in0.syncpol.c1),
c2.eq(self.hdmi_in0.syncpol.c2),
]
for i in range(
6
): # either 5 or 6; 5 if the first pixel is encrypted by the idle cipher; 6 if the cipher has to be pumped before encryption
c0_next = Signal(10)
c1_next = Signal(10)
c2_next = Signal(10)
self.sync.pix_o += [ # extra delay to absorb cross-domain jitter & routing
c0_next.eq(c0),
c1_next.eq(c1),
c2_next.eq(c2),
]
c0 = c0_next
c1 = c1_next
c2 = c2_next
self.sync.pix_o += [ # extra delay to absorb cross-domain jitter & routing
c0_pix_o.eq(c0_next),
c1_pix_o.eq(c1_next),
c2_pix_o.eq(c2_next)
]
rect_on = Signal()
rect_thresh = Signal(8)
self.submodules.rectangle = rectangle = ClockDomainsRenamer("pix_o")(
RectOpening(hdmi_in0_timing))
self.comb += rect_on.eq(rectangle.rect_on)
self.comb += rect_thresh.eq(rectangle.rect_thresh.storage)
self.sync.pix_o += [
# If(rect_on & (hdmi_out0_rgb_d.r >= 128) & (hdmi_out0_rgb_d.g >= 128) & (hdmi_out0_rgb_d.b >= 128),
If(
rect_on & (hdmi_out0_rgb_d.r >= rect_thresh) &
(hdmi_out0_rgb_d.g >= rect_thresh) &
(hdmi_out0_rgb_d.b >= rect_thresh),
# If(rect_on,
self.hdmi_out0_phy.sink.c0.eq(encoder_blu.out),
self.hdmi_out0_phy.sink.c1.eq(encoder_grn.out),
self.hdmi_out0_phy.sink.c2.eq(encoder_red.out),
).Else(
self.hdmi_out0_phy.sink.c0.eq(c0_pix_o),
self.hdmi_out0_phy.sink.c1.eq(c1_pix_o),
self.hdmi_out0_phy.sink.c2.eq(c2_pix_o),
)
]
self.comb += platform.request("fpga_led2", 0).eq(
self.hdmi_in0.clocking.locked) # RX0 green
self.comb += platform.request("fpga_led3", 0).eq(0) # RX0 red
# self.comb += platform.request("fpga_led4", 0).eq(0) # OV0 red
self.comb += platform.request("fpga_led5", 0).eq(
self.hdmi_in1.clocking.locked) # OV0 green
# analyzer ethernet
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
fast_eth = False # fast_eth puts etherbone in 100MHz domain; otherwise try to put it in 50MHz domain.
# 100 MHz domain works but timing closure is hard
# 50 MHz domain should also work but I'm not 100% of the syntax to create the clock domains correctly
if fast_eth:
self.submodules.phy = phy = LiteEthPHYRMII(
platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
mac_address = 0x1337320dbabe
ip_address = "10.0.11.2"
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
convert_ip(ip_address),
int(100e6))
self.submodules.etherbone = LiteEthEtherbone(self.core.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
else:
phy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"),
platform.request("rmii_eth"))
phy = ClockDomainsRenamer("eth")(phy)
mac_address = 0x1337320dbabe
ip_address = "10.0.11.2"
core = LiteEthUDPIPCore(phy,
mac_address,
convert_ip(ip_address),
int(50e6),
with_icmp=True)
core = ClockDomainsRenamer("eth")(core)
self.submodules += phy, core
etherbone_cd = ClockDomain("etherbone")
self.clock_domains += etherbone_cd
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(core.udp,
1234,
mode="master",
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# Attach the VexRiscv debug bus to RAM
self.register_mem("vexriscv_debug", self.mem_map["vexriscv_debug"],
self.cpu_or_bridge.debug_bus, 0x10)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
self.sync += platform.request("fpga_led4", 0).eq(0) # OV0 red
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.51",
with_analyzer=False,
sdram_module="MT48LC16M16",
sdram_init=[],
sdram_data_width=32,
sdram_spd_data=None,
sdram_verbosity=0,
with_i2c=False,
with_sdcard=False,
sim_debug=False,
trace_reset_on=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX Simulation",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
if sdram_spd_data is None:
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(
sdram_spd_data, sdram_clk_freq)
phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=sdram_init)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=False)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
#assert not (with_ethernet and with_etherbone)
if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({
"eth_tx": "ethphy_eth_tx",
"eth_rx": "ethphy_eth_rx"
})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)
self.submodules.i2c = I2CMasterSim(pads)
self.add_csr("i2c")
# SDCard -----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
def __init__(self, platform, connector="pcie", linerate=2.5e9):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# SoCSDRAM ----------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / 100e6)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Ethernet ---------------------------------------------------------------------------------
# phy
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# core
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="172.30.28.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# etherbone bridge
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# GTP PLL ----------------------------------------------------------------------------------
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# Record -------------------------------------------------------------------------------------
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp0_rx"))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.submodules.tx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp1_rx"))
self.tx_dma_recorder.add_csr()
self.add_csr("tx_dma_recorder")
self.comb += [
self.rx_dma_recorder.sink.valid.eq(self.gtp0.source.valid),
self.rx_dma_recorder.sink.data.eq(
self.gtp0.source.payload.raw_bits()),
self.tx_dma_recorder.sink.valid.eq(self.gtp1.source.valid),
self.tx_dma_recorder.sink.data.eq(
self.gtp1.source.payload.raw_bits()),
]
def __init__(self,
*,
args,
sys_clk_freq,
sdram_module_cls,
sdram_module_speedgrade=None,
sdram_module_spd_file=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
self.args = args
self.sys_clk_freq = sys_clk_freq
self.ip_address = ip_address
self.mac_address = mac_address
self.udp_port = udp_port
# Platform ---------------------------------------------------------------------------------
if not args.sim:
self.platform = self.get_platform()
else:
self.platform = SimPlatform()
githash = git.Repo(
'.', search_parent_directories=True).git.rev_parse("HEAD")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
self.platform,
sys_clk_freq,
ident="LiteX Row Hammer Tester SoC on {}, git: {}".format(
self.platform.device, githash),
ident_version=True,
integrated_rom_mode='rw' if args.rw_bios_mem else 'r',
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = self.get_crg()
else:
self.submodules.crg = CRG(self.platform.request('sys_clk'))
# Add dynamic simulation trace control, start enabled
self.platform.add_debug(self, reset=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=self.platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# SDRAM PHY --------------------------------------------------------------------------------
if sdram_module_spd_file is not None:
self.logger.info('Using DRAM module {} data: {}'.format(
colorer('SPD'), sdram_module_spd_file))
with open(sdram_module_spd_file, 'rb') as f:
spd_data = f.read()
module = SDRAMModule.from_spd_data(spd_data, self.sys_clk_freq)
else:
ratio = self.get_sdram_ratio()
self.logger.info('Using DRAM module {} ratio {}'.format(
colorer(sdram_module_cls.__name__), colorer(ratio)))
module = sdram_module_cls(self.sys_clk_freq,
ratio,
speedgrade=sdram_module_speedgrade)
if args.sim:
# Use the hardware platform to retrieve values for simulation
hw_pads = self.get_platform().request('ddram')
core_config = dict(
sdram_module_nb=len(hw_pads.dq) // 8, # number of byte groups
sdram_rank_nb=len(hw_pads.cs_n), # number of ranks
sdram_module=module,
memtype=module.memtype,
)
# Add IO pins
self.platform.add_extension(get_dram_ios(core_config))
phy_settings = get_sdram_phy_settings(
memtype=module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sys_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=module,
settings=phy_settings,
clk_freq=sys_clk_freq,
verbosity=3,
)
else: # hardware
self.submodules.ddrphy = self.get_ddrphy()
self.add_csr("ddrphy")
# SDRAM Controller--------------------------------------------------------------------------
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc, ModuleDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
controller_settings.refresh_cls = SyncableRefresher
assert self.ddrphy.settings.memtype == module.memtype, \
'Wrong DRAM module type: {} vs {}'.format(self.ddrphy.settings.memtype, module.memtype)
self.add_sdram("sdram",
phy=self.ddrphy,
module=module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
controller_settings=controller_settings)
# CPU will report that leveling finished by writing to ddrctrl CSRs
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
self.add_host_bridge()
else: # simulation
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth"))
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=self.ip_address,
mac_address=self.mac_address,
clk_freq=self.sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
self.udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
pattern_data_size = int(args.pattern_data_size, 0)
phy_settings = self.sdram.controller.settings.phy
pattern_data_width = phy_settings.dfi_databits * phy_settings.nphases
pattern_length = pattern_data_size // (pattern_data_width // 8)
assert pattern_data_size % (pattern_data_width//8) == 0, \
'Pattern data memory size must be multiple of {} bytes'.format(pattern_data_width//8)
self.submodules.pattern_mem = PatternMemory(
data_width=pattern_data_width, mem_depth=pattern_length)
self.add_memory(self.pattern_mem.data,
name='pattern_data',
origin=0x20000000)
self.add_memory(self.pattern_mem.addr,
name='pattern_addr',
origin=0x21000000)
self.logger.info(
'{}: Length: {}, Data Width: {}-bit, Address width: {}-bit'.
format(colorer('BIST pattern'), colorer(pattern_length),
colorer(pattern_data_width), colorer(32)))
assert controller_settings.address_mapping == 'ROW_BANK_COL'
row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits
inversion_kwargs = dict(
rowbits=int(self.args.bist_inversion_rowbits, 0),
row_shift=row_offset -
self.sdram.controller.interface.address_align,
)
# Writer
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port, self.pattern_mem,
**inversion_kwargs)
self.writer.add_csrs()
self.add_csr('writer')
# Reader
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port, self.pattern_mem,
**inversion_kwargs)
self.reader.add_csrs()
self.add_csr('reader')
assert pattern_data_width == dram_wr_port.data_width
assert pattern_data_width == dram_rd_port.data_width
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
payload_size = int(args.payload_size, 0)
scratchpad_size = int(args.scratchpad_size, 0)
assert payload_size % 4 == 0, 'Payload memory size must be multiple of 4 bytes'
assert scratchpad_size % (scratchpad_width//8) == 0, \
'Scratchpad memory size must be multiple of {} bytes'.format(scratchpad_width//8)
scratchpad_depth = scratchpad_size // (scratchpad_width // 8)
payload_mem = Memory(32, payload_size // 4)
scratchpad_mem = Memory(scratchpad_width, scratchpad_depth)
self.specials += payload_mem, scratchpad_mem
self.add_memory(payload_mem, name='payload', origin=0x30000000)
self.add_memory(scratchpad_mem,
name='scratchpad',
origin=0x31000000,
mode='r')
self.logger.info('{}: Length: {}, Data Width: {}-bit'.format(
colorer('Instruction payload'), colorer(payload_size // 4),
colorer(32)))
self.logger.info('{}: Length: {}, Data Width: {}-bit'.format(
colorer('Scratchpad memory'), colorer(scratchpad_depth),
colorer(scratchpad_width)))
self.submodules.dfi_switch = DFISwitch(
with_refresh=self.sdram.controller.settings.with_refresh,
dfii=self.sdram.dfii,
refresher_reset=self.sdram.controller.refresher.reset,
)
self.dfi_switch.add_csrs()
self.add_csr('dfi_switch')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi_switch=self.dfi_switch,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
def __init__(self,
with_sdram = False,
with_ethernet = False,
with_etherbone = False,
etherbone_mac_address = 0x10e2d5000001,
etherbone_ip_address = "192.168.1.51",
with_analyzer = False,
sdram_module = "MT48LC16M16",
sdram_init = [],
sdram_data_width = 32,
sdram_verbosity = 0,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteX Simulation", ident_version=True,
l2_reverse = False,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module,
settings = phy_settings,
clk_freq = sdram_clk_freq,
verbosity = sdram_verbosity,
init = sdram_init)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
#assert not (with_ethernet and with_etherbone)
if with_ethernet and with_etherbone:
dw = 8
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=dw,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=dw)
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=dw)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=dw)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=dw)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface = "wishbone",
endianness = self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address = etherbone_mac_address,
ip_address = etherbone_ip_address,
clk_freq = sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.add_csr("analyzer")
def __init__(self,
with_sdram=False,
with_ethernet=False,
ethernet_phy_model="sim",
with_etherbone=False,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.51",
with_analyzer=False,
sdram_module="MT48LC16M16",
sdram_init=[],
sdram_data_width=32,
sdram_spd_data=None,
sdram_verbosity=0,
with_i2c=False,
with_sdcard=False,
with_spi_flash=False,
spi_flash_init=[],
with_gpio=False,
sim_debug=False,
trace_reset_on=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX Simulation",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size and with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
if sdram_spd_data is None:
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(
sdram_spd_data, sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=sdram_init)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=False)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
# Ethernet / Etherbone PHY -----------------------------------------------------------------
if with_ethernet or with_etherbone:
if ethernet_phy_model == "sim":
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
elif ethernet_phy_model == "xgmii":
self.submodules.ethphy = LiteEthPHYXGMII(None,
self.platform.request(
"xgmii_eth", 0),
model=True)
elif ethernet_phy_model == "gmii":
self.submodules.ethphy = LiteEthPHYGMII(None,
self.platform.request(
"gmii_eth", 0),
model=True)
else:
raise ValueError("Unknown Ethernet PHY model:",
ethernet_phy_model)
# Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac",
self.mem_map.get("ethmac", None),
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet MAC
self.submodules.ethmac = ethmac = LiteEthMAC(
phy=self.ethphy,
dw=64 if ethernet_phy_model == "xgmii" else 32,
interface="wishbone",
endianness=self.cpu.endianness)
ethmac_region_size = (
ethmac.rx_slots.read() +
ethmac.tx_slots.read()) * ethmac.slot_size.read()
self.add_memory_region("ethmac",
self.mem_map.get("ethmac", None),
ethmac_region_size,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus,
ethmac_region_size)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
self.add_etherbone(phy=self.ethphy,
ip_address=etherbone_ip_address,
mac_address=etherbone_mac_address)
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)
self.submodules.i2c = I2CMasterSim(pads)
# SDCard -----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.phy.model import LiteSPIPHYModel
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
spiflash_module = S25FL128L(Codes.READ_1_1_4)
if spi_flash_init is None:
platform.add_sources(
os.path.abspath(os.path.dirname(__file__)),
"../build/sim/verilog/iddr_verilog.v")
platform.add_sources(
os.path.abspath(os.path.dirname(__file__)),
"../build/sim/verilog/oddr_verilog.v")
self.submodules.spiflash_phy = LiteSPIPHYModel(spiflash_module,
init=spi_flash_init)
self.add_spi_flash(phy=self.spiflash_phy,
mode="4x",
module=spiflash_module,
with_master=True)
# GPIO --------------------------------------------------------------------------------------
if with_gpio:
self.submodules.gpio = GPIOTristate(platform.request("gpio"),
with_irq=True)
self.irq.add("gpio", use_loc_if_exists=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
def __init__(self,
platform,
connector="pcie",
linerate=2.5e9,
use_gtp=True):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# *********************************************************
# * SoC SDRAM *
# *********************************************************
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# *********************************************************
# * CRG *
# *********************************************************
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq)
# *********************************************************
# * DDR3 *
# *********************************************************
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# *********************************************************
# * Ethernet PHY *
# *********************************************************
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# *********************************************************
# * Ethernet Core *
# *********************************************************
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# *********************************************************
# * Etherbone bridge *
# *********************************************************
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# *********************************************************
# * Timing constraints for Ethernet *
# *********************************************************
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# *********************************************************
# * GTP Refclk *
# *********************************************************
if use_gtp:
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# *********************************************************
# * GTP PLL *
# *********************************************************
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# *********************************************************
# * GTPs *
# *********************************************************
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
gtp.tx_enable = 0
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
else:
gtp0_rx_cd = ClockDomain("gtp0_rx")
self.clock_domains += gtp0_rx_cd
self.comb += [
gtp0_rx_cd.clk.eq(ClockSignal("clk125")),
gtp0_rx_cd.rst.eq(ResetSignal("clk125"))
]
gtp1_rx_cd = ClockDomain("gtp1_rx")
self.clock_domains += gtp1_rx_cd
self.comb += [
gtp1_rx_cd.clk.eq(ClockSignal("clk125")),
gtp1_rx_cd.rst.eq(ResetSignal("clk125"))
]
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp1_rx_cd.clk,
gtp0_rx_cd.clk)
# *********************************************************
# * Time base *
# *********************************************************
time = Signal(32)
time_rx = Signal(32)
time_tx = Signal(32)
self.sync.clk125 += time.eq(time + 1)
self.specials += MultiReg(time, time_rx, "gtp0_rx")
self.specials += MultiReg(time, time_tx, "gtp1_rx")
# *********************************************************
# * RX Capture Pipeline *
# *********************************************************
RX_RING_BUFFER_BASE_ADDRESS = 0
RX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp0_ready
gtp0_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp0.rx_ready,
gtp0_ready, "gtp0_rx")
else:
gtp0_ready.eq(0)
# Request RX DDR3 port
rx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.rx_capture = CapturePipeline(
"gtp0_rx", rx_port, RX_RING_BUFFER_BASE_ADDRESS,
RX_RING_BUFFER_SIZE)
self.add_csr("rx_capture")
self.add_csr("rx_capture_exerciser_mem")
self.add_csr("rx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp0.source.connect(self.rx_capture.sink,
omit={"valid"})
self.comb += [
self.rx_capture.sink.valid.eq(gtp0_ready
| self.rx_capture.simmode),
self.rx_capture.time.eq(time_rx),
]
# *********************************************************
# * TX Capture Pipeline *
# *********************************************************
TX_RING_BUFFER_BASE_ADDRESS = 0x100000
TX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp1_ready
gtp1_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp1.rx_ready,
gtp1_ready, "gtp1_rx")
else:
gtp1_ready.eq(0)
# Request TX DDR3 port
tx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.tx_capture = CapturePipeline(
"gtp1_rx", tx_port, TX_RING_BUFFER_BASE_ADDRESS,
TX_RING_BUFFER_SIZE)
self.add_csr("tx_capture")
self.add_csr("tx_capture_exerciser_mem")
self.add_csr("tx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp1.source.connect(self.tx_capture.sink,
omit={"valid"})
self.comb += [
self.tx_capture.sink.valid.eq(gtp1_ready
| self.tx_capture.simmode),
self.tx_capture.time.eq(time_tx),
]
# *********************************************************
# * Recorder RX/TX *
# *********************************************************
self.comb += [
self.tx_capture.forced.eq(self.rx_capture.record),
self.rx_capture.forced.eq(self.tx_capture.record),
self.tx_capture.trigExt.eq(self.rx_capture.trigOut),
self.rx_capture.trigExt.eq(self.tx_capture.trigOut),
]
# *********************************************************
# * LEDs *
# *********************************************************
led_counter = Signal(32)
self.sync.gtp0_rx += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[24])
self.comb += platform.request("user_led", 1).eq(0)
self.comb += platform.request("user_led", 2).eq(0)
self.comb += platform.request("user_led", 3).eq(0)
def __init__(self,
platform,
connector="pcie",
with_etherbone=False,
with_analyzer=False):
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="USB3SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq)
self.add_wb_master(self.bridge.wishbone)
# Ethernet <--> Wishbone -------------------------------------------------------------------
if with_etherbone:
# phy
self.submodules.eth_phy = LiteEthPHYRGMII(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"))
self.add_csr("eth_phy")
# core
self.submodules.eth_core = LiteEthUDPIPCore(
phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=sys_clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.eth_core.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# USB3 SerDes ------------------------------------------------------------------------------
usb3_serdes = ECP5USB3SerDes(
platform,
sys_clk=self.crg.cd_sys.clk,
sys_clk_freq=sys_clk_freq,
refclk_pads=ClockSignal("clk200"),
refclk_freq=200e6,
tx_pads=platform.request(connector + "_tx"),
rx_pads=platform.request(connector + "_rx"),
channel=1 if connector == "sma" else 0)
self.submodules += usb3_serdes
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(~platform.request("rst_n"))
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
self.add_csr("usb3_core")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(~usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.tx_tseq,
usb3_pipe.ts.tx_ts1,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.tx_done,
# LTSSM
usb3_pipe.ltssm.polling.fsm,
usb3_pipe.ready,
# Endpoints
usb3_serdes.rx_datapath.skip_remover.skip,
usb3_serdes.source,
usb3_serdes.sink,
usb3_pipe.source,
usb3_pipe.sink,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
with_analyzer=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e9/platform.default_clk_period)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation", ident_version=True,
with_uart=False,
**kwargs)
# crg
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# serial
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
# sdram
if with_sdram:
sdram_module = IS42S16160(sys_clk_freq, "1:1")
phy_settings = PhySettings(
memtype="SDR",
dfi_databits=1*16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0
)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_refresh=False))
# reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces
# ethernet
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
# etherbone
if with_etherbone:
# eth phy
self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
# eth core
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq)
if with_ethernet:
etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore)
self.submodules.etherbonecore = etherbonecore
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# analyzer
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
