def __init__(self, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little")) self.add_constant("SIM", None) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, *args, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, platform, core_config): # # PHY -------------------------------------------------------------------------------------- # PHYCore.__init__(self, platform, core_config) # SoC parameters --------------------------------------------------------------------------- soc_args = {} if "soc" in core_config: soc_config = core_config["soc"] for arg in soc_config: if arg in ("csr_map", "interrupt_map", "mem_map"): getattr(self, arg).update(soc_config[arg]) else: soc_args[arg] = soc_config[arg] # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) # PHY ---------------------------------------------------------------------------------- ethphy = LiteEthPHYModel(pads=platform.request("model_eth")) self.submodules.ethphy = ethphy self.add_csr("ethphy") # MAC -------------------------------------------------------------------------------------- self.submodules.ethmac = LiteEthMAC( phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"]) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") # Wishbone Interface ----------------------------------------------------------------------- class _WishboneBridge(Module): def __init__(self, interface): self.wishbone = interface self.wishbone.data_width = 32 bridge = _WishboneBridge(self.platform.request("wishbone")) self.submodules += bridge self.add_wb_master(bridge.wishbone) # Interrupt Interface ---------------------------------------------------------------------- self.comb += self.platform.request("interrupt_request").eq( self.ethmac.ev.irq)
def __init__(self, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, *args, **kwargs) self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteEth bench Simulation", ident_version = True ) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000)
def __init__(self, *args, **kwargs): # Need a larger integrated ROM to fit the BIOS with TFTP support. dict_set_max(kwargs, 'integrated_rom_size', 0x10000) BaseSoC.__init__(self, *args, **kwargs) self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) # FIXME: The sim seems to require ethphy at 18 and ethmac at 19!? self.add_csr("ethphy", csr_id=18) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_csr("ethmac", csr_id=19) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_interupt("ethmac")
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings phy_settings = PhySettings(memtype="SDR", databits=32, dfi_databits=16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) assert not (with_ethernet and with_etherbone ) # FIXME: fix simulator with 2 ethernet interfaces # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # Ethernet --------------------------------------------------------------------------------- if with_etherbone: # Ethernet PHY self.submodules.etherbonephy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("etherbonephy") # Ethernet MAC etherbonecore = LiteEthUDPIPCore(self.etherbonephy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.etherbonecore = etherbonecore # Etherbone self.submodules.etherbone = LiteEthEtherbone( self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, with_sdram = False, with_ethernet = False, with_etherbone = False, etherbone_mac_address = 0x10e2d5000001, etherbone_ip_address = "192.168.1.51", with_analyzer = False, sdram_module = "MT48LC16M16", sdram_init = [], sdram_data_width = 32, sdram_verbosity = 0, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteX Simulation", ident_version=True, l2_reverse = False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings( memtype = sdram_module.memtype, data_width = sdram_data_width, clk_freq = sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel( module = sdram_module, settings = phy_settings, clk_freq = sdram_clk_freq, verbosity = sdram_verbosity, init = sdram_init) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) #assert not (with_ethernet and with_etherbone) if with_ethernet and with_etherbone: dw = 8 etherbone_ip_address = convert_ip(etherbone_ip_address) # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=dw, interface = "hybrid", endianness = self.cpu.endianness, hw_mac = etherbone_mac_address) # SoftCPU self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=dw) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=dw) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=dw) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=dw) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Ethernet --------------------------------------------------------------------------------- elif with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface = "wishbone", endianness = self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address = etherbone_mac_address, ip_address = etherbone_ip_address, clk_freq = sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, init_memories=False, with_sdram=False, sdram_module="MT48LC16M16", sdram_data_width=32, sdram_verbosity=0, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) ram_init = [] if init_memories: ram_init = get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000", "emulator/emulator.bin": "0x01100000", }, "little") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", uart_name="sim", l2_reverse=False, max_sdram_size=0x10000000, # Limit mapped SDRAM to 1GB. integrated_rom_size=0x8000, integrated_main_ram_size=0x00000000 if with_sdram else 0x02000000, # 32MB integrated_main_ram_init=[] if (with_sdram or not init_memories) else ram_init) self.add_constant("SIM", None) # Supervisor ------------------------------------------------------------------------------- self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Machine mode emulator RAM ---------------------------------------------------------------- self.add_memory_region("emulator", self.mem_map["main_ram"] + 0x01100000, 0x4000, type="cached+linker") self.add_constant("ROM_BOOT_ADDRESS", self.bus.regions["emulator"].origin) # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=ram_init) self.add_sdram( "sdram", phy=self.sdrphy, module=sdram_module, origin=self.mem_map["main_ram"], size=0x10000000, # Limit mapped SDRAM to 1GB. l2_cache_reverse=False) # FIXME: skip memtest to avoid corrupting memory self.add_constant("MEMTEST_BUS_SIZE", 0) self.add_constant("MEMTEST_ADDR_SIZE", 0) self.add_constant("MEMTEST_DATA_SIZE", 0) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, init_memories=False, sdram_module="MT48LC16M16", sdram_data_width=32, sdram_verbosity=0, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) ram_init = [] if init_memories: ram_init = get_mem_data( { "images/Image": "0x00000000", "images/rv32.dtb": "0x00ef0000", "images/rootfs.cpio": "0x01000000", "images/opensbi.bin": "0x00f00000" }, "little") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv_smp", cpu_variant="linux", csr_data_width=8, integrated_rom_size=0x8000, uart_name="sim") self.add_constant("SIM") self.add_constant("config_cpu_count", VexRiscvSMP.cpu_count) # for dts generation # Add linker region for OpenSBI self.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker") self.add_constant("ROM_BOOT_ADDRESS", self.bus.regions["opensbi"].origin) # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0c00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # Supervisor ------------------------------------------------------------------------------- self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # SDRAM ------------------------------------------------------------------------------------ sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=ram_init) self.add_sdram("sdram", phy=self.sdrphy, module=sdram_module, origin=self.mem_map["main_ram"], l2_cache_size=0) self.add_constant( "SDRAM_TEST_DISABLE" ) # Skip SDRAM test to avoid corrupting pre-initialized contents. # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, sdram_module, sdram_data_width, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, integrated_rom_size = 0x8000, integrated_sram_size = 0x1000, uart_name = "crossover", l2_size = 0, csr_data_width = 32, **kwargs ) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SDR SDRAM -------------------------------------------------------------------------------- from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings( memtype = sdram_module.memtype, data_width = sdram_data_width, clk_freq = sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel( module = sdram_module, settings = phy_settings, clk_freq = sdram_clk_freq) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Disable Memtest for simulation speedup self.add_constant("MEMTEST_BUS_SIZE", 0) self.add_constant("MEMTEST_ADDR_SIZE", 0) self.add_constant("MEMTEST_DATA_SIZE", 0) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.add_csr("ethphy") # core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", clk_freq = sys_clk_freq) self.submodules.ethcore = ethcore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Record ----------------------------------------------------------------------------------- self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(self.sdram.crossbar.get_port("write", 32)) self.rx_dma_recorder.add_csr() self.add_csr("rx_dma_recorder") self.submodules.tx_dma_recorder = LiteDRAMDMAWriter(self.sdram.crossbar.get_port("write", 32)) self.tx_dma_recorder.add_csr() self.add_csr("tx_dma_recorder") counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += [ self.rx_dma_recorder.sink.valid.eq(1), self.rx_dma_recorder.sink.data.eq(counter), self.tx_dma_recorder.sink.valid.eq(1), self.tx_dma_recorder.sink.data.eq(counter), ]
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), args=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): if not args.sim: platform = arty.Platform(toolchain=toolchain) else: platform = SimPlatform("SIM", _io) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = _CRG(platform, sys_clk_freq, args) else: self.submodules.crg = CRG(platform.request("sys_clk")) # DDR3 SDRAM ------------------------------------------------------------------------------- if not args.sim: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) else: from litedram.gen import get_dram_ios core_config = dict() core_config["sdram_module_nb"] = 2 # Number of byte groups core_config["sdram_rank_nb"] = 1 # Number of ranks core_config['sdram_module'] = getattr(litedram_modules, 'MT41K128M16') core_config["memtype"] = "DDR3" # DRAM type platform.add_extension(get_dram_ios(core_config)) sdram_module = core_config["sdram_module"]( sys_clk_freq, rate={ "DDR2": "1:2", "DDR3": "1:4", "DDR4": "1:4" }[core_config["memtype"]]) from litex.tools.litex_sim import get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings phy_settings = get_sdram_phy_settings( memtype=sdram_module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sdram_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=3, ) class ControllerDynamicSettings(Module, AutoCSR, AutoDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, l2_cache_min_data_width=0, #128 l2_cache_reverse=True, controller_settings=controller_settings) # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: # Ethernet PHY (arty) self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, ip_address=ip_address, mac_address=mac_address, udp_port=udp_port) else: # Ethernet PHY (simulation) self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=ip_address, mac_address=mac_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") if args.sim: self.comb += platform.trace.eq(1) # Rowhammer -------------------------------------------------------------------------------- self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") def add_xram(self, name, origin, mem, mode='rw'): from litex.soc.interconnect import wishbone from litex.soc.integration.soc import SoCRegion ram = wishbone.SRAM(mem, bus=wishbone.Interface(data_width=mem.width), read_only='w' not in mode) ram_bus = wishbone.Interface(data_width=self.bus.data_width) self.submodules += wishbone.Converter(ram_bus, ram.bus) region = SoCRegion(origin=origin, size=mem.width // 8 * mem.depth, mode=mode) self.bus.add_slave(name, ram_bus, region) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( colorer(name), colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: # ------------------------------ writer ------------------------------------ dram_wr_port = self.sdram.crossbar.get_port() self.submodules.writer = Writer(dram_wr_port) self.add_csr('writer') # TODO: Rename as 'pattern_wr_w?' add_xram(self, name='pattern_w0', mem=self.writer.memory_w0, origin=0x20000000) add_xram(self, name='pattern_w1', mem=self.writer.memory_w1, origin=0x21000000) add_xram(self, name='pattern_w2', mem=self.writer.memory_w2, origin=0x22000000) add_xram(self, name='pattern_w3', mem=self.writer.memory_w3, origin=0x23000000) add_xram(self, name='pattern_adr', mem=self.writer.memory_adr, origin=0x24000000) # ----------------------------- reader ------------------------------------- dram_rd_port = self.sdram.crossbar.get_port() self.submodules.reader = Reader(dram_rd_port) self.add_csr('reader') add_xram(self, name='pattern_rd_w0', mem=self.reader.memory_w0, origin=0x30000000) add_xram(self, name='pattern_rd_w1', mem=self.reader.memory_w1, origin=0x31000000) add_xram(self, name='pattern_rd_w2', mem=self.reader.memory_w2, origin=0x32000000) add_xram(self, name='pattern_rd_w3', mem=self.reader.memory_w3, origin=0x33000000) add_xram(self, name='pattern_rd_adr', mem=self.reader.memory_adr, origin=0x34000000) # Payload executor ------------------------------------------------------------------------- if not args.no_payload_executor: # TODO: disconnect bus during payload execution phy_settings = self.sdram.controller.settings.phy scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases scratchpad_size = 2**10 payload_mem = Memory(32, 2**10) scratchpad_mem = Memory(scratchpad_width, scratchpad_size // (scratchpad_width // 8)) self.specials += payload_mem, scratchpad_mem add_xram(self, name='payload', mem=payload_mem, origin=0x35000000) add_xram(self, name='scratchpad', mem=scratchpad_mem, origin=0x36000000, mode='r') self.submodules.payload_executor = PayloadExecutor( mem_payload=payload_mem, mem_scratchpad=scratchpad_mem, dfi=self.sdram.dfii.ext_dfi, dfi_sel=self.sdram.dfii.ext_dfi_sel, nranks=self.sdram.controller.settings.phy.nranks, bankbits=self.sdram.controller.settings.geom.bankbits, rowbits=self.sdram.controller.settings.geom.rowbits, colbits=self.sdram.controller.settings.geom.colbits, rdphase=self.sdram.controller.settings.phy.rdphase, ) self.payload_executor.add_csrs() self.add_csr('payload_executor')
def __init__(self, sdram_module, sdram_data_width, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # ********************************************************* # * SoC SDRAM * # ********************************************************* SoCSDRAM.__init__(self, platform, sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x1000, uart_name="crossover", l2_size=0, csr_data_width=32, **kwargs) # ********************************************************* # * CRG * # ********************************************************* self.submodules.crg = CRG(platform.request("sys_clk")) # ********************************************************* # * SDR SDRAM * # ********************************************************* from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Disable Memtest for simulation speedup self.add_constant("MEMTEST_BUS_SIZE", 0) self.add_constant("MEMTEST_ADDR_SIZE", 0) self.add_constant("MEMTEST_DATA_SIZE", 0) # ********************************************************* # * Ethernet PHY * # ********************************************************* self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.add_csr("ethphy") # ********************************************************* # * Ethernet Core * # ********************************************************* ethcore = LiteEthUDPIPCore(self.ethphy, mac_address=0x10e2d5000000, ip_address="172.30.28.201", clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # ********************************************************* # * Etherbone bridge * # ********************************************************* self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # ********************************************************* # * Ordered Sets Detector / Descrambler RX * # ********************************************************* self.submodules.rx_detector = DetectOrderedSets() self.submodules.rx_descrambler = Descrambler("sys") self.add_csr("rx_descrambler") self.comb += [ #self.gtp0.source.connect(self.rx_detector.sink, omit={"valid"}), self.rx_detector.sink.valid.eq(1), self.rx_detector.source.connect(self.rx_descrambler.sink), ] # ********************************************************* # * Ordered Sets Detector / Descrambler TX * # ********************************************************* self.submodules.tx_detector = DetectOrderedSets() self.submodules.tx_descrambler = Descrambler("sys") self.add_csr("tx_descrambler") self.comb += [ #self.gtp1.source.connect(self.tx_detector.sink, omit={"valid"}), self.tx_detector.sink.valid.eq(1), self.tx_detector.source.connect(self.tx_descrambler.sink), ] # ********************************************************* # * Trigger RX * # ********************************************************* self.submodules.rx_trigger = Trigger("sys") self.comb += [ self.rx_descrambler.source.connect(self.rx_trigger.sink), ] self.add_csr("rx_trigger_mem") self.add_csr("rx_trigger") # ********************************************************* # * Trigger TX * # ********************************************************* self.submodules.tx_trigger = Trigger("sys") self.comb += [ self.tx_descrambler.source.connect(self.tx_trigger.sink), ] self.add_csr("tx_trigger_mem") self.add_csr("tx_trigger") # ********************************************************* # * Recorder RX * # ********************************************************* rx_port = self.sdram.crossbar.get_port("write", 256) STRIDE_MULTIPLIER = 12 rx_recorder = RingRecorder("sys", rx_port, 0, 0x100000, STRIDE_MULTIPLIER) self.submodules.rx_recorder = rx_recorder self.add_csr("rx_recorder") rx_cdc = stream.AsyncFIFO([("address", rx_port.address_width), ("data", rx_port.data_width)], 1024, buffered=True) rx_cdc = ClockDomainsRenamer({"write": "sys", "read": "sys"})(rx_cdc) self.submodules.rx_cdc = rx_cdc self.submodules.rx_dma = LiteDRAMDMAWriter(rx_port) self.comb += [ self.rx_trigger.source.connect(self.rx_recorder.sink), self.rx_trigger.enable.eq(self.rx_recorder.enable), self.rx_recorder.source.connect(self.rx_cdc.sink), self.rx_cdc.source.connect(self.rx_dma.sink), ] # ********************************************************* # * Recorder TX * # ********************************************************* tx_port = self.sdram.crossbar.get_port("write", 256) tx_recorder = RingRecorder("sys", tx_port, 0x100000, 0x100000, STRIDE_MULTIPLIER) self.submodules.tx_recorder = tx_recorder self.add_csr("tx_recorder") tx_cdc = stream.AsyncFIFO([("address", tx_port.address_width), ("data", tx_port.data_width)], 1024, buffered=True) tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "sys"})(tx_cdc) self.submodules.tx_cdc = tx_cdc self.submodules.tx_dma = LiteDRAMDMAWriter(tx_port) self.comb += [ self.tx_trigger.source.connect(self.tx_recorder.sink), self.tx_trigger.enable.eq(self.tx_recorder.enable), self.tx_recorder.source.connect(self.tx_cdc.sink), self.tx_cdc.source.connect(self.tx_dma.sink), ] # ********************************************************* # * Recorder RX/TX * # ********************************************************* self.comb += [ self.tx_recorder.force.eq(self.rx_recorder.enable), self.rx_recorder.force.eq(self.tx_recorder.enable), ]
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), args=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): if not args.sim: platform = arty.Platform(toolchain=toolchain) else: platform = Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = _CRG(platform, sys_clk_freq, args) else: self.submodules.crg = CRG(platform.request("sys_clk")) # DDR3 SDRAM ------------------------------------------------------------------------------- if not args.sim: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) else: from litedram.gen import get_dram_ios core_config = dict() core_config["sdram_module_nb"] = 2 # Number of byte groups core_config["sdram_rank_nb"] = 1 # Number of ranks core_config['sdram_module'] = getattr(litedram_modules, 'MT41K128M16') core_config["memtype"] = "DDR3" # DRAM type platform.add_extension(get_dram_ios(core_config)) sdram_module = core_config["sdram_module"]( sys_clk_freq, rate={ "DDR2": "1:2", "DDR3": "1:4", "DDR4": "1:4" }[core_config["memtype"]]) from litex.tools.litex_sim import get_sdram_phy_settings sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings phy_settings = get_sdram_phy_settings( memtype=sdram_module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sdram_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=3, ) class ControllerDynamicSettings(Module, AutoCSR, AutoDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, l2_cache_min_data_width=0, #128 l2_cache_reverse=True, controller_settings=controller_settings) # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: # Ethernet PHY (arty) self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, ip_address=ip_address, mac_address=mac_address, udp_port=udp_port) else: # Ethernet PHY (simulation) self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=ip_address, mac_address=mac_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # Analyzer --------------------------------------------------------------------------------- # analyzer_signals = [ # self.bus.masters['master0'].stb, # self.bus.masters['master0'].cyc, # self.bus.masters['master0'].adr, # self.bus.masters['master0'].we, # self.bus.masters['master0'].ack, # self.bus.masters['master0'].sel, # self.bus.masters['master0'].dat_w, # self.bus.masters['master0'].dat_r, # ] # from litescope import LiteScopeAnalyzer # self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, # depth = 512, # clock_domain = "sys", # csr_csv = "analyzer.csv") # self.add_csr("analyzer") if args.sim: self.comb += platform.trace.eq(1) # Rowhammer -------------------------------------------------------------------------------- from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker def add_xram(self, name, origin, mem): from litex.soc.interconnect import wishbone from litex.soc.integration.soc import SoCRegion ram_bus = wishbone.Interface(data_width=self.bus.data_width) ram = wishbone.SRAM(mem, bus=ram_bus) self.bus.add_slave( name, ram.bus, SoCRegion(origin=origin, size=mem.width * mem.depth, mode='rw')) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( colorer(name), colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) return # ------------------------------ writer ------------------------------------ memory_w0 = Memory(32, 1024) memory_w1 = Memory(32, 1024) memory_w2 = Memory(32, 1024) memory_w3 = Memory(32, 1024) memory_adr = Memory(32, 1024) add_xram(self, name='pattern_w0', mem=memory_w0, origin=0x20000000) add_xram(self, name='pattern_w1', mem=memory_w1, origin=0x21000000) add_xram(self, name='pattern_w2', mem=memory_w2, origin=0x22000000) add_xram(self, name='pattern_w3', mem=memory_w3, origin=0x23000000) add_xram(self, name='pattern_adr', mem=memory_adr, origin=0x24000000) class Writer(Module, AutoCSR): def __init__(self, dram_port, w0_port, w1_port, w2_port, w3_port, adr_port): self.reset = CSRStorage() self.start = CSRStorage() self.done = CSRStatus() self.count = CSRStorage(size=(32 * 1)) self.mem_base = CSRStorage(size=32) self.mem_mask = CSRStorage(size=32) self.data_mask = CSRStorage(size=32) # patterns dma = LiteDRAMDMAWriter(dram_port, fifo_depth=1) self.submodules += dma cmd_counter = Signal(32) self.comb += [ w0_port.adr.eq(cmd_counter & self.data_mask.storage), w1_port.adr.eq(cmd_counter & self.data_mask.storage), w2_port.adr.eq(cmd_counter & self.data_mask.storage), w3_port.adr.eq(cmd_counter & self.data_mask.storage), adr_port.adr.eq(cmd_counter & self.data_mask.storage), ] self.comb += [ dma.sink.address.eq(self.mem_base.storage + adr_port.dat_r + (cmd_counter & self.mem_mask.storage)), dma.sink.data.eq( Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r, w3_port.dat_r)), ] fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act( "IDLE", If( self.start.storage, NextValue(cmd_counter, 0), NextState("WAIT"), )) fsm.act( "WAIT", If(cmd_counter >= self.count.storage, NextState("DONE")).Else(NextState("RUN"))) fsm.act( "RUN", dma.sink.valid.eq(1), If(dma.sink.ready, NextValue(cmd_counter, cmd_counter + 1), NextState("WAIT"))) fsm.act("DONE", self.done.status.eq(1), If(self.reset.storage, NextState("IDLE"))) dram_port = self.sdram.crossbar.get_port() w0_port = memory_w0.get_port() w1_port = memory_w1.get_port() w2_port = memory_w2.get_port() w3_port = memory_w3.get_port() adr_port = memory_adr.get_port() self.specials += w0_port, w1_port, w2_port, w3_port, adr_port self.submodules.writer = Writer(dram_port, w0_port, w1_port, w2_port, w3_port, adr_port) self.add_csr('writer') # ----------------------------- reader ------------------------------------- memory_rd_w0 = Memory(32, 1024) memory_rd_w1 = Memory(32, 1024) memory_rd_w2 = Memory(32, 1024) memory_rd_w3 = Memory(32, 1024) memory_rd_adr = Memory(32, 1024) add_xram(self, name='pattern_rd_w0', mem=memory_rd_w0, origin=0x30000000) add_xram(self, name='pattern_rd_w1', mem=memory_rd_w1, origin=0x31000000) add_xram(self, name='pattern_rd_w2', mem=memory_rd_w2, origin=0x32000000) add_xram(self, name='pattern_rd_w3', mem=memory_rd_w3, origin=0x33000000) add_xram(self, name='pattern_rd_adr', mem=memory_rd_adr, origin=0x34000000) class Reader(Module, AutoCSR): def __init__(self, dram_port, w0_port, w1_port, w2_port, w3_port, adr_port): self.reset = CSRStorage() self.start = CSRStorage() self.done = CSRStatus() self.count = CSRStorage(size=32) self.pointer = CSRStatus(size=32) self.mem_base = CSRStorage(size=32) self.mem_mask = CSRStorage(size=32) self.data_mask = CSRStorage(size=32) # patterns dma = LiteDRAMDMAReader(dram_port, fifo_depth=1, fifo_buffered=False) self.submodules += dma cmd_counter = Signal(32) self.comb += [ w0_port.adr.eq(cmd_counter & self.data_mask.storage), w1_port.adr.eq(cmd_counter & self.data_mask.storage), w2_port.adr.eq(cmd_counter & self.data_mask.storage), w3_port.adr.eq(cmd_counter & self.data_mask.storage), adr_port.adr.eq(cmd_counter & self.data_mask.storage), ] data_pattern = Signal(32 * 4) self.comb += [ dma.sink.address.eq(self.mem_base.storage + adr_port.dat_r + (cmd_counter & self.mem_mask.storage)), data_pattern.eq( Cat(w0_port.dat_r, w1_port.dat_r, w2_port.dat_r, w3_port.dat_r)), ] fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act( "IDLE", If( self.start.storage, NextValue(cmd_counter, 0), NextValue(self.pointer.status, 0xdeadbeef), NextState("WAIT"), )) fsm.act( "WAIT", If(cmd_counter >= self.count.storage, NextState("DONE")).Else(NextState("WR_ADR"))) fsm.act("WR_ADR", dma.sink.valid.eq(1), If(dma.sink.ready, NextState("RD_DATA"))) fsm.act( "RD_DATA", dma.source.ready.eq(1), If( dma.source.valid, NextValue(cmd_counter, cmd_counter + 1), If(dma.source.data != data_pattern, NextValue(self.pointer.status, cmd_counter)), NextState("WAIT"))) fsm.act("DONE", self.done.status.eq(1), If(self.reset.storage, NextState("IDLE"))) dram_rd_port = self.sdram.crossbar.get_port() w0_port = memory_rd_w0.get_port() w1_port = memory_rd_w1.get_port() w2_port = memory_rd_w2.get_port() w3_port = memory_rd_w3.get_port() adr_port = memory_rd_adr.get_port() self.specials += w0_port, w1_port, w2_port, w3_port, adr_port self.submodules.reader = Reader(dram_rd_port, w0_port, w1_port, w2_port, w3_port, adr_port) self.add_csr('reader')
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000001, etherbone_ip_address="192.168.1.51", with_analyzer=False, sdram_module="MT48LC16M16", sdram_init=[], sdram_data_width=32, sdram_spd_data=None, sdram_verbosity=0, with_i2c=False, with_sdcard=False, sim_debug=False, trace_reset_on=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteX Simulation", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings if sdram_spd_data is None: sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) else: sdram_module = litedram_modules.SDRAMModule.from_spd_data( sdram_spd_data, sdram_clk_freq) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=sdram_init) self.add_sdram("sdram", phy=self.sdrphy, module=sdram_module, origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=False) if sdram_init != []: # Skip SDRAM test to avoid corrupting pre-initialized contents. self.add_constant("SDRAM_TEST_DISABLE") else: # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) #assert not (with_ethernet and with_etherbone) if with_ethernet and with_etherbone: etherbone_ip_address = convert_ip(etherbone_ip_address) # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # SoftCPU self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Ethernet --------------------------------------------------------------------------------- elif with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # IBus (could also just added as self.cpu.ibus) self.cpu.ibus.stb, self.cpu.ibus.cyc, self.cpu.ibus.adr, self.cpu.ibus.we, self.cpu.ibus.ack, self.cpu.ibus.sel, self.cpu.ibus.dat_w, self.cpu.ibus.dat_r, # DBus (could also just added as self.cpu.dbus) self.cpu.dbus.stb, self.cpu.dbus.cyc, self.cpu.dbus.adr, self.cpu.dbus.we, self.cpu.dbus.ack, self.cpu.dbus.sel, self.cpu.dbus.dat_w, self.cpu.dbus.dat_r, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=512, clock_domain="sys", csr_csv="analyzer.csv") self.add_csr("analyzer") # I2C -------------------------------------------------------------------------------------- if with_i2c: pads = platform.request("i2c", 0) self.submodules.i2c = I2CMasterSim(pads) self.add_csr("i2c") # SDCard ----------------------------------------------------------------------------------- if with_sdcard: self.add_sdcard("sdcard", use_emulator=True) # Simulation debugging ---------------------------------------------------------------------- if sim_debug: platform.add_debug(self, reset=1 if trace_reset_on else 0) else: self.comb += platform.trace.eq(1)
def __init__(self, *, args, sys_clk_freq, sdram_module_cls, sdram_module_speedgrade=None, sdram_module_spd_file=None, ip_address="192.168.100.50", mac_address=0x10e2d5000001, udp_port=1234, **kwargs): self.args = args self.sys_clk_freq = sys_clk_freq self.ip_address = ip_address self.mac_address = mac_address self.udp_port = udp_port # Platform --------------------------------------------------------------------------------- if not args.sim: self.platform = self.get_platform() else: self.platform = SimPlatform() githash = git.Repo( '.', search_parent_directories=True).git.rev_parse("HEAD") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__( self, self.platform, sys_clk_freq, ident="LiteX Row Hammer Tester SoC on {}, git: {}".format( self.platform.device, githash), ident_version=True, integrated_rom_mode='rw' if args.rw_bios_mem else 'r', **kwargs) # CRG -------------------------------------------------------------------------------------- if not args.sim: self.submodules.crg = self.get_crg() else: self.submodules.crg = CRG(self.platform.request('sys_clk')) # Add dynamic simulation trace control, start enabled self.platform.add_debug(self, reset=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=self.platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # SDRAM PHY -------------------------------------------------------------------------------- if sdram_module_spd_file is not None: self.logger.info('Using DRAM module {} data: {}'.format( colorer('SPD'), sdram_module_spd_file)) with open(sdram_module_spd_file, 'rb') as f: spd_data = f.read() module = SDRAMModule.from_spd_data(spd_data, self.sys_clk_freq) else: ratio = self.get_sdram_ratio() self.logger.info('Using DRAM module {} ratio {}'.format( colorer(sdram_module_cls.__name__), colorer(ratio))) module = sdram_module_cls(self.sys_clk_freq, ratio, speedgrade=sdram_module_speedgrade) if args.sim: # Use the hardware platform to retrieve values for simulation hw_pads = self.get_platform().request('ddram') core_config = dict( sdram_module_nb=len(hw_pads.dq) // 8, # number of byte groups sdram_rank_nb=len(hw_pads.cs_n), # number of ranks sdram_module=module, memtype=module.memtype, ) # Add IO pins self.platform.add_extension(get_dram_ios(core_config)) phy_settings = get_sdram_phy_settings( memtype=module.memtype, data_width=core_config["sdram_module_nb"] * 8, clk_freq=sys_clk_freq) self.submodules.ddrphy = SDRAMPHYModel( module=module, settings=phy_settings, clk_freq=sys_clk_freq, verbosity=3, ) else: # hardware self.submodules.ddrphy = self.get_ddrphy() self.add_csr("ddrphy") # SDRAM Controller-------------------------------------------------------------------------- class ControllerDynamicSettings(Module, AutoCSR, AutoDoc, ModuleDoc): """Allows to change LiteDRAMController behaviour at runtime""" def __init__(self): self.refresh = CSRStorage( reset=1, description="Enable/disable Refresh commands sending") self.submodules.controller_settings = ControllerDynamicSettings() self.add_csr("controller_settings") controller_settings = ControllerSettings() controller_settings.with_auto_precharge = True controller_settings.with_refresh = self.controller_settings.refresh.storage controller_settings.refresh_cls = SyncableRefresher assert self.ddrphy.settings.memtype == module.memtype, \ 'Wrong DRAM module type: {} vs {}'.format(self.ddrphy.settings.memtype, module.memtype) self.add_sdram("sdram", phy=self.ddrphy, module=module, origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=0, controller_settings=controller_settings) # CPU will report that leveling finished by writing to ddrctrl CSRs self.submodules.ddrctrl = LiteDRAMCoreControl() self.add_csr("ddrctrl") # Ethernet / Etherbone --------------------------------------------------------------------- if not args.sim: self.add_host_bridge() else: # simulation self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth")) self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, ip_address=self.ip_address, mac_address=self.mac_address, clk_freq=self.sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, self.udp_port, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Rowhammer -------------------------------------------------------------------------------- self.submodules.rowhammer_dma = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma) self.add_csr("rowhammer") # Bist ------------------------------------------------------------------------------------- if not args.no_memory_bist: pattern_data_size = int(args.pattern_data_size, 0) phy_settings = self.sdram.controller.settings.phy pattern_data_width = phy_settings.dfi_databits * phy_settings.nphases pattern_length = pattern_data_size // (pattern_data_width // 8) assert pattern_data_size % (pattern_data_width//8) == 0, \ 'Pattern data memory size must be multiple of {} bytes'.format(pattern_data_width//8) self.submodules.pattern_mem = PatternMemory( data_width=pattern_data_width, mem_depth=pattern_length) self.add_memory(self.pattern_mem.data, name='pattern_data', origin=0x20000000) self.add_memory(self.pattern_mem.addr, name='pattern_addr', origin=0x21000000) self.logger.info( '{}: Length: {}, Data Width: {}-bit, Address width: {}-bit'. format(colorer('BIST pattern'), colorer(pattern_length), colorer(pattern_data_width), colorer(32))) assert controller_settings.address_mapping == 'ROW_BANK_COL' row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits inversion_kwargs = dict( rowbits=int(self.args.bist_inversion_rowbits, 0), row_shift=row_offset - self.sdram.controller.interface.address_align, ) # Writer dram_wr_port = self.sdram.crossbar.get_port() self.submodules.writer = Writer(dram_wr_port, self.pattern_mem, **inversion_kwargs) self.writer.add_csrs() self.add_csr('writer') # Reader dram_rd_port = self.sdram.crossbar.get_port() self.submodules.reader = Reader(dram_rd_port, self.pattern_mem, **inversion_kwargs) self.reader.add_csrs() self.add_csr('reader') assert pattern_data_width == dram_wr_port.data_width assert pattern_data_width == dram_rd_port.data_width # Payload executor ------------------------------------------------------------------------- if not args.no_payload_executor: # TODO: disconnect bus during payload execution phy_settings = self.sdram.controller.settings.phy scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases payload_size = int(args.payload_size, 0) scratchpad_size = int(args.scratchpad_size, 0) assert payload_size % 4 == 0, 'Payload memory size must be multiple of 4 bytes' assert scratchpad_size % (scratchpad_width//8) == 0, \ 'Scratchpad memory size must be multiple of {} bytes'.format(scratchpad_width//8) scratchpad_depth = scratchpad_size // (scratchpad_width // 8) payload_mem = Memory(32, payload_size // 4) scratchpad_mem = Memory(scratchpad_width, scratchpad_depth) self.specials += payload_mem, scratchpad_mem self.add_memory(payload_mem, name='payload', origin=0x30000000) self.add_memory(scratchpad_mem, name='scratchpad', origin=0x31000000, mode='r') self.logger.info('{}: Length: {}, Data Width: {}-bit'.format( colorer('Instruction payload'), colorer(payload_size // 4), colorer(32))) self.logger.info('{}: Length: {}, Data Width: {}-bit'.format( colorer('Scratchpad memory'), colorer(scratchpad_depth), colorer(scratchpad_width))) self.submodules.dfi_switch = DFISwitch( with_refresh=self.sdram.controller.settings.with_refresh, dfii=self.sdram.dfii, refresher_reset=self.sdram.controller.refresher.reset, ) self.dfi_switch.add_csrs() self.add_csr('dfi_switch') self.submodules.payload_executor = PayloadExecutor( mem_payload=payload_mem, mem_scratchpad=scratchpad_mem, dfi_switch=self.dfi_switch, nranks=self.sdram.controller.settings.phy.nranks, bankbits=self.sdram.controller.settings.geom.bankbits, rowbits=self.sdram.controller.settings.geom.rowbits, colbits=self.sdram.controller.settings.geom.colbits, rdphase=self.sdram.controller.settings.phy.rdphase, ) self.payload_executor.add_csrs() self.add_csr('payload_executor')
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, with_sdram=False, with_ethernet=False, ethernet_phy_model="sim", with_etherbone=False, etherbone_mac_address=0x10e2d5000001, etherbone_ip_address="192.168.1.51", with_analyzer=False, sdram_module="MT48LC16M16", sdram_init=[], sdram_data_width=32, sdram_spd_data=None, sdram_verbosity=0, with_i2c=False, with_sdcard=False, with_spi_flash=False, spi_flash_init=[], with_gpio=False, sim_debug=False, trace_reset_on=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteX Simulation", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ------------------------------------------------------------------------------------ if not self.integrated_main_ram_size and with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings if sdram_spd_data is None: sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) else: sdram_module = litedram_modules.SDRAMModule.from_spd_data( sdram_spd_data, sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, data_width=sdram_data_width, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=sdram_init) self.add_sdram("sdram", phy=self.sdrphy, module=sdram_module, origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=False) if sdram_init != []: # Skip SDRAM test to avoid corrupting pre-initialized contents. self.add_constant("SDRAM_TEST_DISABLE") else: # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) # Ethernet / Etherbone PHY ----------------------------------------------------------------- if with_ethernet or with_etherbone: if ethernet_phy_model == "sim": self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) elif ethernet_phy_model == "xgmii": self.submodules.ethphy = LiteEthPHYXGMII(None, self.platform.request( "xgmii_eth", 0), model=True) elif ethernet_phy_model == "gmii": self.submodules.ethphy = LiteEthPHYGMII(None, self.platform.request( "gmii_eth", 0), model=True) else: raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model) # Ethernet and Etherbone ------------------------------------------------------------------- if with_ethernet and with_etherbone: etherbone_ip_address = convert_ip(etherbone_ip_address) # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # SoftCPU self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Ethernet --------------------------------------------------------------------------------- elif with_ethernet: # Ethernet MAC self.submodules.ethmac = ethmac = LiteEthMAC( phy=self.ethphy, dw=64 if ethernet_phy_model == "xgmii" else 32, interface="wishbone", endianness=self.cpu.endianness) ethmac_region_size = ( ethmac.rx_slots.read() + ethmac.tx_slots.read()) * ethmac.slot_size.read() self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), ethmac_region_size, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus, ethmac_region_size) if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=etherbone_ip_address, mac_address=etherbone_mac_address) # I2C -------------------------------------------------------------------------------------- if with_i2c: pads = platform.request("i2c", 0) self.submodules.i2c = I2CMasterSim(pads) # SDCard ----------------------------------------------------------------------------------- if with_sdcard: self.add_sdcard("sdcard", use_emulator=True) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.phy.model import LiteSPIPHYModel from litespi.modules import S25FL128L from litespi.opcodes import SpiNorFlashOpCodes as Codes spiflash_module = S25FL128L(Codes.READ_1_1_4) if spi_flash_init is None: platform.add_sources( os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v") platform.add_sources( os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v") self.submodules.spiflash_phy = LiteSPIPHYModel(spiflash_module, init=spi_flash_init) self.add_spi_flash(phy=self.spiflash_phy, mode="4x", module=spiflash_module, with_master=True) # GPIO -------------------------------------------------------------------------------------- if with_gpio: self.submodules.gpio = GPIOTristate(platform.request("gpio"), with_irq=True) self.irq.add("gpio", use_loc_if_exists=True) # Simulation debugging ---------------------------------------------------------------------- if sim_debug: platform.add_debug(self, reset=1 if trace_reset_on else 0) else: self.comb += platform.trace.eq(1) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # IBus (could also just added as self.cpu.ibus) self.cpu.ibus.stb, self.cpu.ibus.cyc, self.cpu.ibus.adr, self.cpu.ibus.we, self.cpu.ibus.ack, self.cpu.ibus.sel, self.cpu.ibus.dat_w, self.cpu.ibus.dat_r, # DBus (could also just added as self.cpu.dbus) self.cpu.dbus.stb, self.cpu.dbus.cyc, self.cpu.dbus.adr, self.cpu.dbus.we, self.cpu.dbus.ack, self.cpu.dbus.sel, self.cpu.dbus.dat_w, self.cpu.dbus.dat_r, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=512, clock_domain="sys", csr_csv="analyzer.csv")
def __init__(self): platform = Platform() sys_clk_freq = int(1e6) self.comb += platform.trace.eq(1) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size = 0x10000, uart_name = "sim") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Etherbone--------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.add_csr("ethphy") # core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", clk_freq = sys_clk_freq) self.submodules.ethcore = ethcore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected # to a SerWB Slave with a SRAM attached. Access to this SRAM is then tested from the main # SoC through SerWB: # +--------+ +------+ +------+ +------+ # | | | +-ck-> | | | # | Test +----+SerWB +-tx->SerWB +----> Test | # | SoC | WB |Master| |Slave | WB | SRAM | # | +<---+ <-rx-+ <----+ | # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ # Pads serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) # Master self.submodules.serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, mode = "master", init_timeout = 128) self.add_csr("serwb_master_phy") # Slave self.submodules.serwb_slave_phy = SERWBPHY( device = platform.device, pads = serwb_slave_pads, mode ="slave", init_timeout = 128) self.add_csr("serwb_slave_phy") # Wishbone Slave serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave") self.submodules += serwb_master_core # Wishbone Master serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master") self.submodules += serwb_slave_core # Wishbone SRAM self.submodules.serwb_sram = wishbone.SRAM(8192) self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus)