def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
mode = "ycbcr422"
if mode == "ycbcr422":
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port,
"ycbcr422")
elif mode == "rgb":
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=32,
cd="pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port, "rgb")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix.clk, 10.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# hdmi in 0
self.submodules.hdmi_in0 = HDMIIn(
platform.request("hdmi_in", 0),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
# hdmi in 1
self.submodules.hdmi_in1 = HDMIIn(
platform.request("hdmi_in", 1),
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512)
# hdmi out 0
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out", 0),
self.sdram.crossbar.get_port(
mode="read",
dw=16,
cd="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096)
# hdmi out 1 : Share clocking with hdmi_out0 since no PLL_ADV left.
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="hdmi_out1_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=4096,
external_clocking=self.hdmi_out0.driver.clocking)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST crg_pll_adv LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
# We have CDC to go from sys_clk to pixel domain
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
def add_framebuffer(self, video_settings):
platform = self.platform
assert platform.device[:4] == "xc7a"
dram_port = self.sdram.crossbar.get_port(mode="read",
data_width=32,
clock_domain="pix",
reverse=True)
framebuffer = VideoOut(device=platform.device,
pads=platform.request("hdmi_out"),
dram_port=dram_port)
self.submodules.framebuffer = framebuffer
self.add_csr("framebuffer")
clocking = framebuffer.driver.clocking
platform.add_period_constraint(clocking.cd_pix.clk,
1e9 / video_settings["pix_clk"])
platform.add_period_constraint(
clocking.cd_pix5x.clk, 1e9 / (5 * video_settings["pix_clk"]))
platform.add_false_path_constraints(
self.crg.cd_sys.clk, framebuffer.driver.clocking.cd_pix.clk,
framebuffer.driver.clocking.cd_pix5x.clk)
self.add_constant("litevideo_pix_clk", video_settings["pix_clk"])
self.add_constant("litevideo_h_active", video_settings["h-active"])
self.add_constant("litevideo_h_blanking",
video_settings["h-blanking"])
self.add_constant("litevideo_h_sync", video_settings["h-sync"])
self.add_constant("litevideo_h_front_porch",
video_settings["h-front-porch"])
self.add_constant("litevideo_v_active", video_settings["v-active"])
self.add_constant("litevideo_v_blanking",
video_settings["v-blanking"])
self.add_constant("litevideo_v_sync", video_settings["v-sync"])
self.add_constant("litevideo_v_front_porch",
video_settings["v-front-porch"])
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out", 0)
dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
hdmi_out0_pads,
dram_port,
mode="ycbcr422",
fifo_depth=4096,
)
self.hdmi_out0.submodules.i2c = i2c.I2C(hdmi_out0_pads)
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
def __init__(self, platform, **kwargs):
base_cls.__init__(self, platform, **kwargs)
# hdmi out 0
dram_port = self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out", 0),
dram_port,
mode="ycbcr422",
fifo_depth=4096)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST PLL_ADV LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
analyzer_signals = [
#self.hdmi_out0.core.timing.hactive,
#self.hdmi_out0.core.timing.vactive,
#self.hdmi_out0.core.timing.active,
#self.hdmi_out0.core.timing.hcounter,
#self.hdmi_out0.core.timing.vcounter,
self.hdmi_out0.core.timing.sink.valid,
self.hdmi_out0.core.timing.sink.ready,
self.hdmi_out0.core.timing.source.valid,
self.hdmi_out0.core.timing.source.ready,
#self.hdmi_out0.core.dma.offset,
self.hdmi_out0.core.dma.sink.valid,
self.hdmi_out0.core.dma.sink.ready,
self.hdmi_out0.core.dma.source.valid,
self.hdmi_out0.core.dma.source.ready,
dram_port.counter,
dram_port.rdata_chunk,
dram_port.cmd_buffer.sink.valid,
dram_port.cmd_buffer.sink.ready,
dram_port.cmd_buffer.source.valid,
dram_port.cmd_buffer.source.ready,
dram_port.rdata_buffer.sink.valid,
dram_port.rdata_buffer.sink.ready,
dram_port.rdata_buffer.source.valid,
dram_port.rdata_buffer.source.ready,
dram_port.rdata_converter.sink.valid,
dram_port.rdata_converter.sink.ready,
dram_port.rdata_converter.source.valid,
dram_port.rdata_converter.source.ready,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
pix_freq = 148.50e6
# hdmi in
hdmi_in0_pads = platform.request("hdmi_in")
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk)
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk,
period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
# hdmi out
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="hdmi_out0_pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix5x.clk,
period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
# hdmi over
self.comb += [
platform.request("hdmi_sda_over_up").eq(0),
platform.request("hdmi_sda_over_dn").eq(0),
platform.request("hdmi_hdp_over").eq(0),
]
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
mode = "ycbcr422"
if mode == "ycbcr422":
hdmi_out0_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port,
"ycbcr422",
)
elif mode == "rgb":
hdmi_out0_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=32,
clock_domain="pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port,
"rgb",
)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.hdmi_out0.driver.clocking.cd_pix.clk, 10.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.hdmi_out0.driver.clocking.cd_pix.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
def add_framebuffer(self):
platform = self.platform
assert platform.device[:4] == "xc7a"
dram_port = self.sdram.crossbar.get_port(mode="read",
data_width=32,
clock_domain="pix",
reverse=True)
framebuffer = VideoOut(device=platform.device,
pads=platform.request("hdmi_out"),
dram_port=dram_port)
self.submodules.framebuffer = framebuffer
self.add_csr("framebuffer")
framebuffer.driver.clocking.cd_pix.clk.attr.add("keep")
framebuffer.driver.clocking.cd_pix5x.clk.attr.add("keep")
platform.add_period_constraint(
framebuffer.driver.clocking.cd_pix.clk, 1e9 / 74.25e6)
platform.add_period_constraint(
framebuffer.driver.clocking.cd_pix5x.clk, 1e9 / (5 * 74.25e6))
platform.add_false_path_constraints(
self.crg.cd_sys.clk, framebuffer.driver.clocking.cd_pix.clk,
framebuffer.driver.clocking.cd_pix5x.clk)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
mode = "ycbcr422"
if mode == "ycbcr422":
dw = 16
elif mode == "rgb":
dw = 32
else:
raise SystemError("Unknown pixel mode.")
pix_freq = 148.50e6
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in")
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7")
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.comb += [
self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
hdmi_in0_pads.txen.eq(1)
]
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk,
period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out")
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=dw,
cd="hdmi_out0_pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
hdmi_out0_pads,
hdmi_out0_dram_port,
mode=mode,
fifo_depth=4096)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk)
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1 * pix_freq))
self.platform.add_period_constraint(
self.hdmi_out0.driver.clocking.cd_pix5x.clk,
period_ns(5 * pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
def __init__(self,
platform,
with_cpu=True,
with_sdram=True,
with_etherbone=True,
with_pcie=True,
with_sdram_dmas=False,
with_hdmi_in0=True,
with_hdmi_out0=True):
sys_clk_freq = int(100e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv" if with_cpu else None,
cpu_variant="lite",
l2_size=128,
csr_data_width=32,
with_uart=with_cpu,
uart_name="crossover",
integrated_rom_size=0x8000 if with_cpu else 0x0000,
integrated_main_ram_size=0x1000 if not with_sdram else 0x0000,
ident="NeTV2 LiteX SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DNA --------------------------------------------------------------------------------------
self.submodules.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("dna")
# XADC -------------------------------------------------------------------------------------
self.submodules.xadc = XADC()
self.add_csr("xadc")
# ICAP -------------------------------------------------------------------------------------
self.submodules.icap = ICAP(platform)
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
self.add_csr("icap")
# Flash ------------------------------------------------------------------------------------
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
self.add_csr("flash")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# ethphy
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# ethcore
self.submodules.ethcore = LiteEthUDPIPCore(
phy=self.ethphy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=self.clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.ethcore.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 50e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 50e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
# PHY ----------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
data_width=64,
bar0_size=0x20000)
platform.add_false_path_constraint(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint -----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# Wishbone bridge ----------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0 ---------------------------------------------------------------------------------
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma0")
# DMA1 ---------------------------------------------------------------------------------
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_csr("pcie_dma1")
self.add_constant("DMA_CHANNELS", 2)
# MSI ----------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# FIXME : Dummy counter capture, connect to HDMI In ------------------------------------
pcie_dma0_counter = Signal(32)
self.sync += [
self.pcie_dma0.sink.valid.eq(1),
If(self.pcie_dma0.sink.ready,
pcie_dma0_counter.eq(pcie_dma0_counter + 1)),
self.pcie_dma0.sink.data.eq(pcie_dma0_counter)
]
pcie_dma1_counter = Signal(32)
self.sync += [
self.pcie_dma1.sink.valid.eq(1),
If(self.pcie_dma1.sink.ready,
pcie_dma1_counter.eq(pcie_dma1_counter + 2)),
self.pcie_dma1.sink.data.eq(pcie_dma1_counter)
]
# SDRAM DMAs -------------------------------------------------------------------------------
if with_sdram_dmas:
self.submodules.sdram_reader = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_reader.add_csr()
self.add_csr("sdram_reader")
self.submodules.sdram_writer = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.sdram_writer.add_csr()
self.add_csr("sdram_writer")
# HDMI In 0 --------------------------------------------------------------------------------
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
pads=hdmi_in0_pads,
dram_port=self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6)
# HDMI Out 0 -------------------------------------------------------------------------------
if with_hdmi_out0:
self.submodules.hdmi_out0 = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out", 0),
dram_port=self.sdram.crossbar.get_port(
mode="read",
data_width=16,
clock_domain="hdmi_out0_pix",
reverse=True),
mode="ycbcr422",
fifo_depth=512)
self.add_csr("hdmi_out0")
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
def __init__(self, platform,
with_sdram=True,
with_ethernet=False,
with_etherbone=True,
with_sdcard=True,
with_pcie=False,
with_hdmi_in0=False, with_hdmi_out0=False,
with_hdmi_in1=False, with_hdmi_out1=False,
with_interboard_communication=False):
assert not (with_pcie and with_interboard_communication)
sys_clk_freq = int(100e6)
sd_freq = int(100e6)
SoCSDRAM.__init__(self, platform, sys_clk_freq,
#cpu_type="vexriscv", l2_size=32,
cpu_type=None, l2_size=32,
#csr_data_width=8, csr_address_width=14,
csr_data_width=32, csr_address_width=14,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
integrated_main_ram_size=0x8000 if not with_sdram else 0,
ident="NeTV2 LiteX Test SoC", ident_version=True,
reserve_nmi_interrupt=False)
# crg
self.submodules.crg = CRG(platform, sys_clk_freq)
# dnax
self.submodules.dna = dna.DNA()
# xadc
self.submodules.xadc = xadc.XADC()
# icap
self.submodules.icap = ICAP(platform)
# flash
self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6))
# sdram
if with_sdram:
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6)
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# ethernet
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# etherbone
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq)
self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master"))
self.add_wb_master(self.cpu.wishbone.bus)
#self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
#self.add_wb_master(self.etherbone.wishbone.bus)
self.crg.cd_eth.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_eth.clk)
# sdcard
self.submodules.sdclk = SDClockerS7()
self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device)
self.submodules.sdcore = SDCore(self.sdphy)
self.submodules.sdtimer = Timer()
self.submodules.bist_generator = BISTBlockGenerator(random=True)
self.submodules.bist_checker = BISTBlockChecker(random=True)
self.comb += [
self.sdcore.source.connect(self.bist_checker.sink),
self.bist_generator.source.connect(self.sdcore.sink)
]
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq)
self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq)
self.crg.cd_sys.clk.attr.add("keep")
self.sdclk.cd_sd.clk.attr.add("keep")
self.sdclk.cd_sd_fb.clk.attr.add("keep")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sdclk.cd_sd.clk,
self.sdclk.cd_sd_fb.clk)
# pcie
if with_pcie:
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000)
self.add_wb_master(self.pcie_bridge.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# interboard communication
if with_interboard_communication:
self.clock_domains.cd_refclk = ClockDomain()
self.submodules.refclk_pll = refclk_pll = S7PLL()
refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6)
refclk_pll.create_clkout(self.cd_refclk, 125e6)
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# qpll
qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9)
print(qpll)
self.submodules += qpll
# gtp
gtp = GTP(qpll,
platform.request("interboard_comm_tx"),
platform.request("interboard_comm_rx"),
sys_clk_freq,
clock_aligner=True, internal_loopback=False)
self.submodules += gtp
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# send counter to other-board
self.comb += [
gtp.encoder.k[0].eq(1),
gtp.encoder.d[0].eq((5 << 5) | 28),
gtp.encoder.k[1].eq(0),
gtp.encoder.d[1].eq(counter[26:])
]
# receive counter and display it on leds
self.comb += [
platform.request("user_led", 3).eq(gtp.rx_ready),
platform.request("user_led", 4).eq(gtp.decoders[1].d[0]),
platform.request("user_led", 5).eq(gtp.decoders[1].d[1])
]
gtp.cd_tx.clk.attr.add("keep")
gtp.cd_rx.clk.attr.add("keep")
platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# hdmi in 0
if with_hdmi_in0:
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
if with_hdmi_out0:
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# hdmi in 1
if with_hdmi_in1:
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk),
for clk in [self.hdmi_in1.clocking.cd_pix.clk,
self.hdmi_in1.clocking.cd_pix1p25x.clk,
self.hdmi_in1.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6))
# hdmi out 1
if with_hdmi_out1:
hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
platform.request("hdmi_out", 1),
hdmi_out1_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
# led blinking (sys)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
# led blinking (pcie)
if with_pcie:
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# led blinking (sdcard)
if with_sdcard:
sd_counter = Signal(32)
self.sync.sd += sd_counter.eq(sd_counter + 1)
self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
mode = "ycbcr422"
if mode == "ycbcr422":
dw = 16
elif mode == "rgb":
dw = 32
else:
raise SystemError("Unknown pixel mode.")
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
)
self.submodules.hdmi_in0_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in0.clocking.clk_input, measure_period=self.clk_freq)
# hdmi in 1
hdmi_in1_pads = platform.request("hdmi_in", 1)
self.submodules.hdmi_in1 = HDMIIn(
hdmi_in1_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
)
self.submodules.hdmi_in1_freq = freq_measurement.FrequencyMeasurement(
self.hdmi_in1.clocking.clk_input, measure_period=self.clk_freq)
# hdmi out 0
hdmi_out0_pads = platform.request("hdmi_out", 0)
hdmi_out0_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=dw,
clock_domain="hdmi_out0_pix",
reverse=True,
)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
hdmi_out0_pads,
hdmi_out0_dram_port,
mode=mode,
fifo_depth=4096,
)
self.hdmi_out0.submodules.i2c = i2c.I2C(hdmi_out0_pads)
# hdmi out 1 : Share clocking with hdmi_out0 since no PLL_ADV left.
hdmi_out1_pads = platform.request("hdmi_out", 1)
hdmi_out1_dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=dw,
clock_domain="hdmi_out1_pix",
reverse=True,
)
self.submodules.hdmi_out1 = VideoOut(
platform.device,
hdmi_out1_pads,
hdmi_out1_dram_port,
mode=mode,
fifo_depth=4096,
external_clocking=self.hdmi_out0.driver.clocking,
)
self.hdmi_out1.submodules.i2c = i2c.I2C(hdmi_out1_pads)
# all PLL_ADV are used: router needs help...
platform.add_platform_command("""INST crg_pll_adv LOC=PLL_ADV_X0Y0;""")
# FIXME: Fix the HDMI out so this can be removed.
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command(
"""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
# We have CDC to go from sys_clk to pixel domain
platform.add_platform_command(
"""
NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
""",
pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out1.driver.clocking.cd_pix.clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
self.add_interrupt("hdmi_in0")
self.add_interrupt("hdmi_in1")
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, csr_data_width=32, *args, **kwargs)
sys_clk_freq = int(100e6)
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
bar0_size=32 * 1024 * 1024)
self.add_csr("pcie_phy")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000)
self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone)
self.add_wb_master(self.wb_swap.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_loopback=True)
self.add_csr("pcie_dma0")
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.add_csr("hdmi_in0_freq")
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=1024,
device="xc7",
split_mmcm=True)
self.add_csr("hdmi_in0")
self.add_csr("hdmi_in0_edid_mem")
self.add_interrupt("hdmi_in0")
self.comb += self.hdmi_in0_freq.clk.eq(
self.hdmi_in0.clocking.cd_pix.clk),
for clk in [
self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk
]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(
platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read",
dw=16,
cd="hdmi_out0_pix",
reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
self.add_csr("hdmi_out0")
for clk in [
self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk
]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
