def __init__(self, eth_port=0, toolchain="diamond"):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(133e6)
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type=None,
with_uart=False,
csr_data_width=32,
ident="Versa ECP5 test SoC",
ident_version=True)
# crg
self.submodules.crg = RGMIITestCRG(platform, sys_clk_freq)
# ethernet mac/udp/ip stack
ethphy = LiteEthPHYRGMII(platform.request("eth_clocks", eth_port),
platform.request("eth", eth_port))
ethcore = LiteEthUDPIPCore(ethphy,
mac_address=0x10e2d5000000,
ip_address=convert_ip("192.168.1.50"),
clk_freq=sys_clk_freq,
with_icmp=True)
self.submodules += ethphy, ethcore
ethphy.crg.cd_eth_rx.clk.attr.add("keep")
ethphy.crg.cd_eth_tx.clk.attr.add("keep")
platform.add_period_constraint(ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6)
platform.add_period_constraint(ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
def main():
with open("README.md") as f:
description = [str(f.readline()) for i in range(7)]
parser = argparse.ArgumentParser(
description="".join(description[1:]),
formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (to SRAM)")
args = parser.parse_args()
if not args.build and not args.load:
parser.print_help()
if args.build:
print("[build]...")
os.makedirs("build/gateware", exist_ok=True)
os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(_usb3_io)
soc = USB3SoC(platform)
builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
builder.build()
if args.load:
print("[load]...")
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def __init__(self, toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(75e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv",
integrated_rom_size=0x8000,
**kwargs)
# crg
if not self.integrated_main_ram_size:
crg = DDR3TestCRG(platform, sys_clk_freq)
else:
crg = RGMIITestCRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
def __init__(self, **kwargs):
platform = versa_ecp5.Platform(toolchain="diamond")
platform.add_extension(_ddram_io)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type="picorv32",
l2_size=32,
integrated_rom_size=0x8000,
**kwargs)
# crg
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = ecp5ddrphy.ECP5DDRPHY(
platform.request("ddram"), sys_clk_freq=sys_clk_freq)
sdram_module = MT41K64M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def main():
parser = argparse.ArgumentParser(
description="LiteICLink transceiver example on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--connector",
default="pcie",
help="Connector: pcie (default) or sma")
parser.add_argument("--linerate",
default="2.5e9",
help="Linerate (default: 2.5e9)")
args = parser.parse_args()
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(_transceiver_io)
soc = SerDesTestSoC(platform,
connector=args.connector,
linerate=float(args.linerate))
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
def main():
if "load" in sys.argv[1:]:
load()
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(_transceiver_io)
soc = SerDesTestSoC(platform)
builder = Builder(soc, output_dir="build")
builder.build(build_name="versa_ecp5")
def main():
if "load" in sys.argv[1:]:
load()
exit()
else:
platform = versa_ecp5.Platform(toolchain="trellis")
soc = UDPLoopback(platform)
builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
vns = builder.build()
def __init__(self,
sys_clk_freq=int(75e6),
device="LFE5UM5G",
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
toolchain="trellis",
**kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# FIXME: adapt integrated rom size for Microwatt
if kwargs.get("cpu_type", None) == "microwatt":
kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Versa ECP5",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def main():
if "load" in sys.argv[1:]:
load()
os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(_usb3_io)
soc = USB3SoC(platform)
builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
vns = builder.build()
def __init__(self, **kwargs):
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C32M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, toolchain="diamond"):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type=None,
l2_size=32,
with_uart=None,
csr_data_width=32,
ident="Versa ECP5 test SoC",
ident_version=True)
# crg
crg = DDR3TestCRG(platform, sys_clk_freq)
self.submodules.crg = crg
# uart
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
# analyzer
analyzer_signals = [
self.ddrphy.dfi.p0, self.ddrphy.datavalid, self.ddrphy.burstdet
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 128)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_constant("ECP5DDRPHY", None)
ddrphy_init = ECP5DDRPHYInit(self.crg, self.ddrphy)
self.submodules += ddrphy_init
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, toolchain="diamond", **kwargs):
sys_clk_freq = int(100e6)
platform = versa_ecp5.Platform(toolchain=toolchain)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SerDes RefClk ----------------------------------------------------------------------------
refclk_pads = platform.request("refclk", 1)
refclk = Signal()
self.specials.extref0 = Instance(
"EXTREFB",
i_REFCLKP=refclk_pads.p,
i_REFCLKN=refclk_pads.n,
o_REFCLKO=refclk,
p_REFCK_PWDNB="0b1",
p_REFCK_RTERM="0b1", # 100 Ohm
)
self.extref0.attr.add(("LOC", "EXTREF0"))
# SerDes PLL -------------------------------------------------------------------------------
serdes_pll = SerDesECP5PLL(refclk,
refclk_freq=156.25e6,
linerate=2.5e9)
self.submodules += serdes_pll
# SerDes -----------------------------------------------------------------------------------
tx_pads = platform.request("sma_tx")
rx_pads = platform.request("sma_rx")
serdes = SerDesECP5(serdes_pll,
tx_pads,
rx_pads,
channel=1,
data_width=20)
serdes.add_stream_endpoints()
self.submodules += serdes
platform.add_period_constraint(serdes.txoutclk, 1e9 / 125e6)
platform.add_period_constraint(serdes.rxoutclk, 1e9 / 125e6)
# Test -------------------------------------------------------------------------------------
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)
# K28.5 and slow counter --> TX
self.comb += [
serdes.sink.valid.eq(1),
serdes.sink.ctrl.eq(0b01),
serdes.sink.data[0:8].eq((5 << 5) | 28),
serdes.sink.data[8:16].eq(counter[26:]),
]
# RX (slow counter) --> Leds
self.sync.rx += [
serdes.rx_align.eq(1),
serdes.source.ready.eq(1),
platform.request("user_led", 4).eq(serdes.source.data[8]),
platform.request("user_led", 5).eq(serdes.source.data[9]),
platform.request("user_led", 6).eq(serdes.source.data[10]),
platform.request("user_led", 7).eq(serdes.source.data[11]),
]
# Leds -------------------------------------------------------------------------------------
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 0).eq(sys_counter[26])
rx_counter = Signal(32)
self.sync.rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 1).eq(rx_counter[26])
tx_counter = Signal(32)
self.sync.tx += tx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 2).eq(tx_counter[26])
