def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain: radiant (default) or prjoxide") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--serial", default="serial", help="UART Pins: serial (default, requires R15 and R17 to be soldered) or serial_pmod[0-2]") parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash") builder_args(parser) soc_core_args(parser) oxide_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), toolchain = args.toolchain, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {} builder.build(**builder_kargs, run=args.build) if args.load: prog = soc.platform.create_programmer(args.prog_target) prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): parser = argparse.ArgumentParser( description="LiteX SoC on Crosslink-NX VIP Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain: radiant (default) or prjoxide") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument( "--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1") parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash") builder_args(parser) soc_core_args(parser) oxide_args(parser) args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), hyperram=args.with_hyperram, toolchain=args.toolchain, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {} builder.build(**builder_kargs, run=args.build) if args.load: prog = soc.platform.create_programmer(args.prog_target) prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).") target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") target_group.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).") target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") builder_args(parser) soc_core_args(parser) oxide_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), hyperram = args.with_hyperram, toolchain = args.toolchain, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {} builder.build(**builder_kargs, run=args.build) if args.load: prog = soc.platform.create_programmer(args.prog_target) prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser( description="LiteX SoC on Crosslink-NX Eval Board") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).") target_group.add_argument( "--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).") target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") target_group.add_argument( "--serial", default="serial", help= "UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2])." ) target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") builder_args(parser) soc_core_args(parser) oxide_args(parser) args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), device=args.device, toolchain=args.toolchain, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {} builder.build(**builder_kargs, run=args.build) if args.load: prog = soc.platform.create_programmer(args.prog_target) prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def hps_soc_args(parser: argparse.ArgumentParser): builder_args(parser) radiant_build_args(parser) oxide_args(parser)