def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) try: self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) except ConstraintError: pass try: self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) except ConstraintError: pass
def __init__(self, device="LIFCL-40-9BG400C", toolchain="radiant", **kwargs): # Accept "LIFCL" for backwards compatibility. # LIFCL just means Crosslink-NX so we can expect every # Crosslink-NX Evaluation Board to have a LIFCL part. if device == "LIFCL": device == "LIFCL-40-9BG400C" assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"] LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
def main(): parser = argparse.ArgumentParser( description="LiteDRAM standalone core generator") builder_args(parser) parser.set_defaults(output_dir="build") parser.add_argument("config", help="YAML config file") parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation") args = parser.parse_args() core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader) # Convert YAML elements to Python/LiteX -------------------------------------------------------- for k, v in core_config.items(): replaces = {"False": False, "True": True, "None": None} for r in replaces.keys(): if v == r: core_config[k] = replaces[r] if "clk_freq" in k: core_config[k] = float(core_config[k]) if k == "sdram_module": core_config[k] = getattr(litedram_modules, core_config[k]) if k == "sdram_phy": core_config[k] = getattr(litedram_phys, core_config[k]) # Generate core -------------------------------------------------------------------------------- if args.sim: platform = SimPlatform("", io=[]) elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: platform = LatticePlatform( "LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: allow other devices. elif core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: platform = XilinxPlatform("", io=[], toolchain="vivado") elif core_config["sdram_phy"] in [ litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY ]: platform = XilinxPlatform("", io=[], toolchain="vivado") else: raise ValueError("Unsupported SDRAM PHY: {}".format( core_config["sdram_phy"])) builder_arguments = builder_argdict(args) builder_arguments["compile_gateware"] = False soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) builder = Builder(soc, **builder_arguments) builder.build(build_name="litedram_core", regular_comb=False) if soc.cpu_type is not None: init_filename = "mem.init" os.system("mv {} {}".format( os.path.join(builder.gateware_dir, init_filename), os.path.join(builder.gateware_dir, "litedram_core.init"), )) replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"), init_filename, "litedram_core.init")
def main(): parser = argparse.ArgumentParser( description="LiteDRAM standalone core generator") parser.add_argument("config", help="YAML config file") args = parser.parse_args() core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader) # Convert YAML elements to Python/LiteX -------------------------------------------------------- for k, v in core_config.items(): replaces = {"False": False, "True": True, "None": None} for r in replaces.keys(): if v == r: core_config[k] = replaces[r] if "clk_freq" in k: core_config[k] = float(core_config[k]) if k == "sdram_module": core_config[k] = getattr(litedram_modules, core_config[k]) if k == "sdram_phy": core_config[k] = getattr(litedram_phys, core_config[k]) # Generate core -------------------------------------------------------------------------------- if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: platform = LatticePlatform("", io=[], toolchain="diamond") elif core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: platform = XilinxPlatform("", io=[], toolchain="vivado") else: raise ValueError("Unsupported SDRAM PHY: {}".format( core_config["sdram_phy"])) soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, integrated_sram_size=0x1000) builder = Builder(soc, output_dir="build", compile_gateware=False) vns = builder.build(build_name="litedram_core", regular_comb=False) # Prepare core (could be improved) def replace_in_file(filename, _from, _to): # Read in the file with open(filename, "r") as file: filedata = file.read() # Replace the target string filedata = filedata.replace(_from, _to) # Write the file out again with open(filename, 'w') as file: file.write(filedata) if soc.cpu_type is not None: init_filename = "mem.init" os.system( "mv build/gateware/{} build/gateware/litedram_core.init".format( init_filename)) replace_in_file("build/gateware/litedram_core.v", init_filename, "litedram_core.init")
def __init__(self, revision="7.1"): assert revision in ["6.0", "7.1"] self.revision = revision device = { "6.0": "LFE5U-25F-6BG256C", "7.1": "LFE5U-25F-6BG256C" }[revision] io = {"6.0": _io_v6_0, "7.1": _io_v7_1}[revision] connectors = { "6.0": _connectors_v6_0, "7.1": _connectors_v7_1 }[revision] LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain="trellis")
def __init__(self, revision="0.2", device="25F", toolchain="trellis", **kwargs): assert revision in ["0.1", "0.2"] self.revision = revision io = {"0.1": _io_r0_1, "0.2": _io_r0_2}[revision] connectors = { "0.1": _connectors_r0_1, "0.2": _connectors_r0_2 }[revision] LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, toolchain=toolchain, **kwargs)
def request(self, *args, **kwargs): if "serial" in args: print( "two 0 Ω resistors shoud be populated on R34 and R35 and " "the FT2232H should be configured to UART with virtual COM on " "port B") if "ext_clk50" in args: print("an oscillator must be populated on X5") return LatticePlatform.request(self, *args, **kwargs)
def __init__(self, board="i5", revision="7.0", toolchain="trellis"): if board == "i5": assert revision in ["7.0"] self.revision = revision device = {"7.0": "LFE5U-25F-6BG381C"}[revision] io = {"7.0": _io_v7_0}[revision] connectors = {"7.0": _connectors_v7_0}[revision] if board == "i9": assert revision in ["7.2"] self.revision = revision device = {"7.2": "LFE5U-45F-6BG381C"}[revision] io = {"7.2": _io_v7_2}[revision] connectors = {"7.2": _connectors_v7_2}[revision] LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
def request(self, *args, **kwargs): import time if "serial" in args: msg = "FT2232H will be used as serial, make sure that:\n" msg += " -the hardware has been modified: R22 and R23 should be removed, two 0 Ω resistors shoud be populated on R34 and R35.\n" msg += " -the chip is configured as UART with virtual COM on port B (With FTProg or https://github.com/trabucayre/fixFT2232_ecp5evn)." print(msg) time.sleep(2) if "ext_clk50" in args: print("An oscillator must be populated on X5.") time.sleep(2) return LatticePlatform.request(self, *args, **kwargs)
def __init__(self): LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
def __init__(self, device="LFE5U-45F", **kwargs): LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5U-25F-8BG381C", _io, **kwargs)
def __init__(self, device="LFE5U-45F", revision="2.0", **kwargs): assert device in ["LFE5U-25F", "LFE5U-45F", "LFE5U-85F"] assert revision in ["1.7", "2.0"] _io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision] LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
def __init__(self): LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)
def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
def request(self, *args, **kwargs): return LatticePlatform.request(self, *args, **kwargs)
def __init__(self): LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", _io, _connectors, toolchain="icestorm")
def __init__(self, toolchain="trellis", **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381I", _io, _connectors, toolchain=toolchain, **kwargs)
def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
def generate_one(t, mw_init): print("Generating target:", t) # Muck with directory path build_dir = make_new_dir(build_top_dir, t) t_dir = make_new_dir(gen_dir, t) # Grab config file cfile = os.path.join(gen_src_dir, t + ".yml") core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader) ### TODO: Make most stuff below a function in litedram gen.py and ### call it rather than duplicate it ### # Convert YAML elements to Python/LiteX for k, v in core_config.items(): replaces = {"False": False, "True": True, "None": None} for r in replaces.keys(): if v == r: core_config[k] = replaces[r] if "clk_freq" in k: core_config[k] = float(core_config[k]) if k == "sdram_module": core_config[k] = getattr(litedram_modules, core_config[k]) if k == "sdram_phy": core_config[k] = getattr(litedram_phys, core_config[k]) # Override values for mw_init if mw_init: core_config["cpu"] = None core_config["csr_expose"] = True core_config["csr_align"] = 64 # Generate core if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") elif core_config["sdram_phy"] in [ litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY ]: platform = XilinxPlatform("", io=[], toolchain="vivado") else: raise ValueError("Unsupported SDRAM PHY: {}".format( core_config["sdram_phy"])) soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) vns = builder.build(build_name="litedram_core", regular_comb=False) # Grab generated gatewar dir gw_dir = os.path.join(build_dir, "gateware") # Generate init-cpu.txt if any and generate init code if none cpu = core_config["cpu"] if mw_init: src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl") src_init_file = build_init_code(build_dir) else: write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu) src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl") src_init_file = os.path.join(gw_dir, "mem.init") # Copy generated files to target dir, amend them if necessary core_file = os.path.join(gw_dir, "litedram_core.v") dst_init_file = os.path.join(t_dir, "litedram_core.init") dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl") replace_in_file(core_file, "mem.init", "litedram_core.init") shutil.copy(core_file, t_dir) shutil.copyfile(src_init_file, dst_init_file) shutil.copyfile(src_wrap_file, dst_wrap_file)
def __init__(self, device="LFE5UM5G", **kwargs): assert device in ["LFE5UM5G", "LFE5UM"] LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, _connectors, **kwargs)
def __init__(self): LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm")
def __init__(self, device="LIFCL", **kwargs): assert device in ["LIFCL"] LatticePlatform.__init__(self, device + "-40-9BG400C", _io, _connectors, toolchain="radiant", **kwargs)
def __init__(self): LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
def __init__(self, toolchain="icestorm"): LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", _io, _connectors, toolchain=toolchain) self.add_extension(serial)
def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment)
def __init__(self): LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm") self.add_extension(serial)
def __init__(self, toolchain="icestorm"): LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain)
def __init__(self, revision="7.0"): assert revision in ["6.1", "7.0"] self.revision = revision device = {"6.1": "LFE5U-25F-6BG381C", "7.0": "LFE5U-25F-6BG256C"}[revision] io = {"6.1": _io_v6_1, "7.0": _io_v7_0}[revision] LatticePlatform.__init__(self, device, io, toolchain="trellis")
def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)