def get_verilog(self, fragment, **kwargs): return verilog.convert( fragment, self.constraint_manager.get_io_signals(), create_clock_domains=False, **kwargs)
def get_verilog(self, fragment, **kwargs): return verilog.convert(fragment, platform=self, **kwargs)
self.comb += [lfsr.ce.eq(self._dma.data.stb), self._dma.data.ack.eq(1)] err_cnt = self._error_count.status self.sync += [ If(self._reset.re, err_cnt.eq(0)).Elif( self._dma.data.stb, If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1))) ] def get_csrs(self): return [self._magic, self._reset, self._error_count ] + self._dma.get_csrs() class _LFSRTB(Module): def __init__(self, *args, **kwargs): self.submodules.dut = LFSR(*args, **kwargs) self.comb += self.dut.ce.eq(1) def do_simulation(self, selfp): print("{0:032x}".format(selfp.dut.o)) if __name__ == "__main__": from litex.gen.fhdl import verilog from litex.gen.sim.generic import run_simulation lfsr = LFSR(3, 4, [3, 2]) print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o})) run_simulation(_LFSRTB(128), ncycles=20)
yield dut.axi_lite.r.ready.eq(1) yield dut.axi_lite.ar.addr.eq(addr) while (yield dut.axi_lite.ar.ready != 1): yield yield dut.axi_lite.ar.valid.eq(0) while (yield dut.axi_lite.r.valid != 1): yield yield dut.axi_lite.r.ready.eq(0) yield from read_w(0x0) r = (yield dut.axi_lite.r.data) for _ in range(8): yield yield from read_w(0x800) r = (yield dut.axi_lite.r.data) for _ in range(8): yield # print("Running simulation...") # t = Top() # run_simulation(t, testbench_write_read(t), vcd_name='axi-read.vcd') print("Exporting lxwrap.v...") t = Top() verilog.convert(t, ios=t.ios).write('lxwrap.v') t.print_map()
if actions["clean"]: subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: csr_csv = cpu_interface.get_csr_csv(csr_regions, constants, memory_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-core"]: ios = soc.get_ios() if not isinstance(soc, _Fragment): soc = soc.get_fragment() platform.finalize(soc) so = { NoRetiming: XilinxNoRetiming, MultiReg: XilinxMultiReg, AsyncResetSynchronizer: XilinxAsyncResetSynchronizer } v_output = verilog.convert(soc, ios, name="litesata", special_overrides=so) v_output.write("build/litesata.v") if actions["build-bitstream"]: build_kwargs = dict((k, autotype(v)) for k, v in args.build_option) vns = platform.build(soc, build_name=build_name, **build_kwargs) if hasattr(soc, "do_exit") and vns is not None: if hasattr(soc.do_exit, '__call__'): soc.do_exit(vns) if actions["load-bitstream"]: prog = platform.create_programmer() prog.load_bitstream("build/" + build_name + platform.bitstream_ext)