def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
clk25 = platform.request("clk25")
platform.add_period_constraint(clk25, 1e9 / 25e6)
self.submodules.pll = pll = S6PLL(speedgrade=-2)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=270)
self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE",
p_INIT=0,
p_SRTYPE="SYNC",
i_D0=0,
i_D1=1,
i_S=0,
i_R=0,
i_CE=1,
i_C0=self.cd_sys.clk,
i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_hdmi5x = ClockDomain()
# # #
# Clk / Rst
clk32 = platform.request("clk32")
# PLL
self.submodules.pll = pll = S6PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk32, 32e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=90)
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
#platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
pll.create_clkout(self.cd_hdmi, 1 * 40e6)
pll.create_clkout(self.cd_hdmi5x, 5 * 40e6)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk32 = platform.request("clk32")
# PLL
self.submodules.pll = pll = S6PLL(speedgrade=-1)
pll.register_clkin(clk32, 32e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=90)
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
# # #
clk25 = platform.request("clk25")
platform.add_period_constraint(clk25, 1e9 / 25e6)
self.submodules.pll = pll = S6PLL(speedgrade=-2)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
clk25 = platform.request("clk25")
self.submodules.pll = pll = S6PLL(speedgrade=-2)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
def __init__(self, p, sys_clk_freq, f_sample_tx=None):
# ----------------------------
# Clock and Reset Generation
# ----------------------------
xtal_pads = p.request(p.default_clk_name)
xtal = Signal()
self.specials += DifferentialInput(xtal_pads.p, xtal_pads.n, xtal)
xtal_f = 1e9 / p.default_clk_period
rst = p.request("cpu_reset")
cds = [("cd_sys", sys_clk_freq)]
if f_sample_tx is not None:
cds.append(("cd_sample_tx", f_sample_tx))
for cd, f in cds:
setattr(self.clock_domains, cd, ClockDomain(cd))
pll = S6PLL(speedgrade=-3)
self.comb += pll.reset.eq(rst)
pll.register_clkin(xtal, xtal_f)
pll.create_clkout(getattr(self, cd), f)
self.submodules += pll
if f_sample_tx is not None:
# Provide a ENC clock signal on SMA_GPIO
enc_out = Signal()
self.specials += Instance(
"ODDR2",
o_Q=enc_out,
i_C0=ClockSignal("sample_tx"),
i_C1=~ClockSignal("sample_tx"),
i_CE=1,
i_D0=1,
i_D1=0
)
p.add_extension(
# Connect GPIO_SMA on SP605 with CLK input on 1525A
[("ENC_CLK", 0,
Subsignal("p", Pins("SMA_GPIO:P")),
Subsignal("n", Pins("SMA_GPIO:N")),
# Note: the LTC eval board needs to be modded
# to accept a differential clock
IOStandard("LVDS_25")
)]
)
gpio_pads = p.request("ENC_CLK")
self.specials += DifferentialOutput(enc_out, gpio_pads.p, gpio_pads.n)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
#self.clock_domains.cd_sys2x = ClockDomain()
#self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
# PLL
self.submodules.pll = pll = S6PLL(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset")
| ~platform.request("cclk"))
pll.register_clkin(platform.request("clk50"), 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
#pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
#pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
ClockSignal("sys_ps"))