def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"botones": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
#botones con interrupcion
bot = Cat(*[platform.request("boton", i) for i in range(8)])
self.submodules.botones = btnintrupt(bot)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
#Memoria SD
self.submodules.SD = SPIMaster(platform.request("sd_spi"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(
self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
# SD
self.submodules.SD = SD(platform.request("SD"),
platform.request("butt"), "csr")
# LCD
self.submodules.LCD = SPIMaster(platform.request("LCD"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.spi_sd = SPIMaster(platform.request("SD"))
self.comb += platform.request("uCD").eq(0x1)
def __init__(self, platform):
sys_clk_freq = int(32e6)
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=32e6,
csr_data_width=32,
ident="GameSnake",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
#Button_interrupt
button_in = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = btnintrupt(button_in)
#lcd parallel
self.submodules.lcd_test = LCD_i80(sys_clk_freq)
self.comb += [
platform.request("db").eq(self.lcd_test.db_),
platform.request("cs").eq(self.lcd_test.cs_),
platform.request("rs").eq(self.lcd_test.rs_),
platform.request("rd").eq(self.lcd_test.rd_),
platform.request("wr").eq(self.lcd_test.wr_),
platform.request("rst").eq(self.lcd_test.rst_),
]
# SD_spi
self.submodules.spi_sd = SPIMaster(platform.request("SD"))
self.comb += platform.request("uCD").eq(0x1)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(9)])
self.submodules.leds = Led(user_leds)
# Spi
self.submodules.spi = SPIMaster(platform.request("spi_master"))
# control_lcd
control_lcd = Cat(
*[platform.request("control_lcd", i) for i in range(3)])
self.submodules.ctrllcd = gpio.GPIOOut(control_lcd)
self.submodules.i2s = I2S(platform.request("i2s_"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.SD = SPIMaster(platform.request("sd_spi"))
#sdcard
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=100e6,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width=32,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
def add_oled(self):
pads = self.platform.request("oled_spi")
pads.miso = Signal()
self.submodules.oled_spi = SPIMaster(pads, 8, self.sys_clk_freq, 8e6)
self.oled_spi.add_clk_divider()
self.submodules.oled_ctl = GPIOOut(self.platform.request("oled_ctl"))
def __init__(self, pads):
spi_pads = Record([("cs_n", 1), ("clk", 1), ("mosi", 1)])
self.submodules.spi = SPIMaster(spi_pads, 8, div=16, cpha=0)
self.comb += [
pads.sclk.eq(spi_pads.clk),
pads.sdin.eq(spi_pads.mosi)
]
def __init__(self, pads):
spi_pads = Record([("cs_n", 1), ("clk", 1), ("mosi", 1)])
self.submodules.spi = SPIMaster(spi_pads, 8, div=16, cpha=0)
self.comb += [
pads.sclk.eq(spi_pads.clk),
pads.sdin.eq(spi_pads.mosi)
]
self.submodules.gpio = GPIOOut(Cat(pads.res, pads.dc, pads.vbat, pads.vdd))
def flash(self):
self.sh = Scanhead(board.Platform(), test=True)
self.sh.submodules.master = SPIMaster(self.sh.spi,
data_width=8,
sys_clk_freq=100e6,
spi_clk_freq=5e6,
with_csr=False)
self.spi = FakeSpi(self.sh.master)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"buttons": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=32 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(8)])
self.submodules.buttons = btnintrupt(user_buttons)
#LedAzul
user_led = Cat(*[platform.request("led_GB", i) for i in range(1)])
self.submodules.led_GB = Led(user_led)
#spiLCD
user_control = Cat(
*[platform.request("pantalla_control", i) for i in range(3)])
self.submodules.pantalla_spi = SPIMaster(
platform.request("pantalla_spi"))
self.submodules.pantalla_control = Led(user_control)
#spiSd
user_control_sd = Cat(
*[platform.request("sdcard_v", i) for i in range(1)])
self.submodules.sdcard_spi = SPIMaster(platform.request("sdcard_spi"))
self.submodules.sdcard_v = Led(user_control_sd)
print(SoCCore.interrupt_map)
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoC init (No CPU, we controlling the SoC with UART)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="My first System On Chip",
ident_version=True,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self):
pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1),
("miso", 1)])
self.submodules.master = SPIMaster(pads,
data_width=32,
sys_clk_freq=100e6,
spi_clk_freq=5e6,
with_csr=False)
self.submodules.slave = SPISlave(pads, data_width=32)
def add_spi_master(self):
self.submodules.spi_master = SPIMaster(
pads=self.platform.request("dw1000_spi"),
data_width=8,
sys_clk_freq=self.sys_clk_freq,
spi_clk_freq=2e6,
manual_cs=True)
self.spi_master.add_csr(with_loopback=True)
self.spi_master.add_clk_divider()
self.add_csr("spi_master")
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCMini (No CPU, we are controlling the SoC over UART)
SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32,
ident="My first LiteX System On Chip", ident_version=True)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width = 32,
sys_clk_freq = sys_clk_freq,
spi_clk_freq = 1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self):
pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1),
("miso", 1)])
self.submodules.master = SPIMaster(pads,
data_width=8,
sys_clk_freq=100e6,
spi_clk_freq=5e6,
with_csr=False)
self.led = Signal()
self.submodules.ledprogram = LEDProgram(pads,
self.led,
memdepth=16)
def __init__(self, sys_clk_freq, pins):
self.submodules.dc = GPIOOut(pins.dc)
self.submodules.backligth = GPIOOut(pins.bl_led)
self.submodules.reset = GPIOOut(pins.reset)
pins.miso = Signal()
self.submodules.spi = SPIMaster(
pads=pins,
data_width=8,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=4e6,
)
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq,
spi_clk_freq)
self.specials += Instance("USRMCLK",
i_USRMCLKI=spi.pads.clk,
i_USRMCLKTS=0)
if hasattr(pads, "vpp"):
pads.vpp.reset = 1
if hasattr(pads, "hold"):
pads.hold.reset = 1
if hasattr(pads, "cs_n"):
self.comb += pads.cs_n.eq(spi.pads.cs_n)
self.comb += [pads.mosi.eq(spi.pads.mosi), spi.pads.miso.eq(pads.miso)]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
csr_data_width=32,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=35 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
#RS y RST LCD
rs = platform.request("lcd_rs")
self.submodules.rs = Led(rs)
rst = platform.request("lcd_rst")
rst = 1
# Buttons
bttn = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = button_intr(bttn)
#GPO
self.submodules.GPO = Led(platform.request("GPO", 0))
#SD
self.submodules.SD = SPIMaster(platform.request("SD_spi"))
# LCD
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
def test_spi_master_xfer_loopback(self):
def generator(dut):
yield dut.loopback.eq(1)
yield dut.mosi.eq(0xdeadbeef)
yield dut.length.eq(32)
yield dut.start.eq(1)
yield
yield dut.start.eq(0)
yield
while (yield dut.done) == 0:
yield
self.assertEqual((yield dut.miso), 0xdeadbeef)
dut = SPIMaster(pads=None,
data_width=32,
sys_clk_freq=100e6,
spi_clk_freq=5e6,
with_csr=False)
run_simulation(dut, generator(dut))
def __init__(self, platform):
sys_clk_freq = int(32e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=32e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# Spi
self.submodules.spi = SPIMaster(platform.request("spi_master"))
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq,
spi_clk_freq)
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spi.pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
if hasattr(pads, "vpp"):
pads.vpp.reset = 1
if hasattr(pads, "hold"):
pads.hold.reset = 1
if hasattr(pads, "cs_n"):
self.comb += pads.cs_n.eq(spi.pads.cs_n)
self.comb += [pads.mosi.eq(spi.pads.mosi), spi.pads.miso.eq(pads.miso)]
def test_spi_master_xfer_loopback_32b_16b(self):
def generator(dut):
yield dut.loopback.eq(1)
yield dut.mosi.eq(0xbeef)
yield dut.length.eq(16)
yield dut.start.eq(1)
yield
yield dut.start.eq(0)
yield
while (yield dut.done) == 0:
yield
yield
self.assertEqual(hex((yield dut.miso)), hex(0xbeef))
dut = SPIMaster(pads=None,
data_width=32,
sys_clk_freq=100e6,
spi_clk_freq=5e6,
with_csr=False,
mode="aligned")
run_simulation(dut, generator(dut))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self, platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC", ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
#sdcard
#self.submodules.sdcard = SDCore(platform.request("sd_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self,
sys_clk_freq=int(50e6),
x5_clk_freq=None,
toolchain="trellis",
**kwargs):
from litex.build.generic_platform import Subsignal, Pins, IOStandard
platform = ecp5_evn.Platform(toolchain=toolchain)
self._add_extentions(platform)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_main_ram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
self.submodules.crg = crg
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
#self.submodules.hyperram = HyperRAMX2(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# ADC RAM
self.add_ram("adc_sram", self.mem_map["adc_sram"], 8 * 4 * 4096)
# ADC --------------------------------------------------------------------------------------
adc_ctrl = platform.request("adc_ctrl", 0)
adc_data = platform.request("adc_data", 0)
self.add_csr("adc")
self.submodules.adc = ADC3321_DMA(adc_ctrl, adc_data)
self.add_wb_master(self.adc.wishbone)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# ADC SPI bus ------------------------------------------------------------------------------
# max SPI frequency is 20 MHz
self.add_csr("adc_spi")
self.submodules.adc_spi = SPIMaster(platform.request("adc_spi", 1),
24,
sys_clk_freq,
int(sys_clk_freq / 80),
with_csr=True)
# Wishbone Debug
# added io to platform, serial_wb
self.submodules.bridge = UARTWishboneBridge(platform.request(
"serial_wb", 1),
sys_clk_freq,
baudrate=3000000)
self.add_wb_master(self.bridge.wishbone)
self.add_csr("analyzer")
analyzer_signals = [
# self.adc.adc_frontend.adc_buffer.adc_dout0,
# self.adc.adc_frontend.adc_buffer.adc_dout1,
# self.adc.adc_frontend.adc_buffer.i_fclk,
self.adc.adc_frontend_a.i_we,
# self.adc.adc_frontend.i_re,
# self.adc.adc_frontend.o_readable,
# self.adc.adc_frontend.adc_buffer.o_dout,
# self.adc.adc_frontend.adc_buffer.pulser.output,
# self.adc.adc_frontend.adc_buffer.fifo.din,
# self.adc.adc_frontend.o_dout,
]
#t = Signal()
#self.comb += [t.eq(clk_outputs.hr_p)]
analyzer_depth = 512 # samples
analyzer_clock_domain = "sys"
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
analyzer_depth,
clock_domain=analyzer_clock_domain)
# put pulser on pin..
debug_pins = platform.request("debug_pins")
self.comb += debug_pins.dbg1.eq(
self.adc.adc_frontend_a.adc_buffer.pulser.output)
def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([(
"serial",
0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)])
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
rst=platform.request("sys_rst"))
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SPI Master
if with_spi_master:
platform.add_extension([(
"spi_master",
0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
)])
self.submodules.spi_master = SPIMaster(
pads=platform.request("spi_master"),
data_width=spi_master_data_width,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=spi_master_clk_freq,
)
self.add_csr("spi_master")
# PWM
if with_pwm:
platform.add_extension([("pwm", 0, Pins(1))])
self.submodules.pwm = PWM(platform.request("pwm"))
self.add_csr("pwm")
# GPIO
if with_gpio:
platform.add_extension([("gpio", 0, Pins(gpio_width))])
self.submodules.gpio = GPIOTristate(platform.request("gpio"))
self.add_csr("gpio")
# Wishbone Master
if kwargs["bus"] == "wishbone":
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# AXI-Lite Master
if kwargs["bus"] == "axi":
axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
wb_bus = wishbone.Interface()
axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
self.submodules += axi2wb
self.bus.add_master(master=wb_bus)
platform.add_extension(axi_bus.get_ios("axi"))
axi_pads = platform.request("axi")
self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)
def __init__(self):
pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)])
self.submodules.master = SPIMaster(pads, data_width=8,
sys_clk_freq=100e6, spi_clk_freq=5e6,
with_csr=False)
self.submodules.spimemmap = SpiMemmapping(pads, 8)
def test_spi_master_syntax(self):
spi_master = SPIMaster(pads=None,
data_width=32,
sys_clk_freq=100e6,
spi_clk_freq=5e6)
self.assertEqual(hasattr(spi_master, "pads"), 1)
