def load_rom(self, filename, delay=0):
from litex.soc.integration.common import get_mem_data
rom_data = get_mem_data(filename, "little")
for i, data in enumerate(rom_data):
self.bus.write(self.bus.mems.rom.base + 4 * i, data)
print(f"{(i+1)*4}/{len(rom_data*4)} bytes\r", end="")
time.sleep(delay)
print("")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--cfu", required=True, help="Specify file containing CFU Verilog module")
parser.add_argument("--sim-trace", action="store_true", help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start", default=0, help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end", default=-1, help="Stop tracing at this time in picoseconds")
parser.add_argument("--run", action="store_true", help="Whether to run the simulation")
parser.add_argument("--bin", help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(
csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+debug', # don't specify 'cfu' here
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
soc_kwargs = soc_sdram_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(
integrated_main_ram_size = 32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug = True,
**soc_kwargs)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# get the CFU version, plus the CFU itself and a wrapper
# ...since we're using stock litex, it doesn't know about the Cfu variants, so we need to use "external_variant"
if args.cfu:
assert 'full' in args.cpu_variant
var = "FullCfuDebug" if ('debug' in args.cpu_variant) else "FullCfu"
vexriscv = "../third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv"
soc.cpu.use_external_variant(f"{vexriscv}/verilog/VexRiscv_{var}.v")
soc.platform.add_source(args.cfu)
soc.platform.add_source(f"{vexriscv}/verilog/wrapVexRiscv_{var}.v")
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(
build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
def run(args, builder, build_kwargs, target_name):
# Generate files in the build directory
configure_generated_files(builder, args, target_name)
# Build & run
if not args.sim: # hardware
builder.build(**build_kwargs, run=args.build)
else: # simulation
sim_kwargs = get_sim_kwargs(args)
builder.build(**build_kwargs, run=args.build, **sim_kwargs)
if args.docs:
doc.generate_docs(builder.soc,
base_dir="build/documentation",
project_name="LiteX Row Hammer Tester",
author="Antmicro")
if args.load:
prog = builder.soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir,
builder.soc.build_name + ".bit"))
if args.load_bios:
assert args.rw_bios_mem, 'BIOS memory must be writible'
from rowhammer_tester.scripts.utils import RemoteClient, memwrite
wb = RemoteClient()
wb.open()
from litex.soc.integration.common import get_mem_data
bios_bin = os.path.join(builder.software_dir, "bios", "bios.bin")
rom_data = get_mem_data(bios_bin, "little")
print(
f"Loading BIOS from: {bios_bin} starting at 0x{wb.mems.rom.base:08x} ..."
)
print('Stopping CPU')
wb.regs.ctrl_reset.write(0b10) # cpu_rst
memwrite(wb, rom_data, base=wb.mems.rom.base)
wb.read(wb.mems.rom.base)
print('Rebooting CPU')
wb.regs.ctrl_reset.write(0)
wb.close()
if args.flash:
prog = builder.soc.platform.create_programmer()
prog.flash(
0,
os.path.join(builder.gateware_dir,
builder.soc.build_name + ".bin"))
def __init__(self, ip="192.168.19.70", **kwargs):
super().__init__(with_ethernet=True, **kwargs)
if kwargs.get('uart_name') == "crossover+bridge":
self.uart.add_auto_tx_flush(self.sys_clk_freq)
print("added_flush")
self.platform.add_extension(marble.break_off_pmod)
self.user_leds = self.platform.request("pmod0")
self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, 0x12345678abcd,
convert_ip(ip),
clk_freq=self.sys_clk_freq)
self.add_csr("udp_core")
self.udp_port = udp_port = self.udp_core.udp.crossbar.get_port(4321, 8)
ddr_wr_port, ddr_rd_port = self.sdram.crossbar.get_port("write"), self.sdram.crossbar.get_port("read")
REAL_ADC = True
if REAL_ADC:
self.add_zest()
adc_dw = self.zest.dw
adc_source = self.zest.source
self.submodules.async_fifo = async_fifo = ClockDomainsRenamer(
{"write": "adc", "read": "sys"}
)(AsyncFIFO([("data", adc_dw)], depth=8, buffered=True))
self.comb += [
async_fifo.sink.data.eq(self.zest.source.data),
async_fifo.sink.valid.eq(self.zest.source.valid),
async_fifo.source.ready.eq(1)
]
self.adc_source = adc_source = async_fifo.source
else:
adc_dw = 64
self.submodules.adcs = adcs = ADCStream(1, adc_dw)
self.adc_source = adc_source = adcs.source
self.submodules.data_pipe = DataPipe(ddr_wr_port, ddr_rd_port, udp_port, adc_source, adc_dw)
self.add_csr("data_pipe")
self.add_rom("bootrom",
origin=0x20000000,
size=2**14,
contents=get_mem_data("firmware/app.bin", endianness="little"))
self.add_constant("ROM_BOOT_ADDRESS", 0x20000000)
def main():
soc_cls = BaseSoC
cpu = VexRiscv
parser = argparse.ArgumentParser(description="LiteX SoC")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--build_gateware", action='store_true')
parser.add_argument("--yosys", action="store_true")
parser.add_argument("--sim", action="store_true")
parser.add_argument("--run", action="store_true")
args = parser.parse_args()
builder_kwargs = builder_argdict(args)
soc_kwargs = soc_core_argdict(args)
platform = sim_platform2.Platform() if args.sim else platform1.Platform()
output_dir = builder_kwargs['output_dir'] = 'build'
fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin")
soc_kwargs['integrated_rom_size'] = 32 * 1024
soc_kwargs["integrated_main_ram_size"] = 16 * 1024
try:
soc_kwargs['integrated_main_ram_init'] = get_mem_data(
fw_file, cpu.endianness)
except OSError:
pass
soc = BaseSoC(platform,
cpu=cpu,
sim=args.sim,
output_dir=output_dir,
**soc_kwargs)
builder = Builder(soc, **builder_kwargs)
builder.add_software_package("firmware",
src_dir=os.path.join(os.getcwd(), 'src',
'firmware'))
if args.sim:
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
builder.build(run=False, sim_config=sim_config, opt_level='O3')
if args.run:
builder.build(build=False, sim_config=sim_config)
else:
builder.build(run=args.build_gateware,
synth_mode="yosys" if args.yosys else "vivado")
def load_rom(wb, filename):
from litex.soc.integration.common import get_mem_data
rom_data = get_mem_data(filename, "little")
for i, data in enumerate(rom_data):
wb.write(wb.mems.rom.base + 4 * i, data)
def main():
patch_cpu_variant()
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--sim-trace",
action="store_true",
help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start",
default=0,
help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end",
default=-1,
help="Stop tracing at this time in picoseconds")
parser.add_argument("--run",
action="store_true",
help="Whether to run the simulation")
parser.add_argument("--separate-arena",
action="store_true",
help="Add arena mem region at 0x60000000")
parser.add_argument("--cfu-mport", action="store_true", help="Add ports between arena and CFU " \
"(implies --separate-arena)")
parser.add_argument("--bin",
help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+cfu+debug',
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
# cfu_mport implies separate_arena
if args.cfu_mport:
args.separate_arena = True
copy_cpu_variant_if_needed(args.cpu_variant)
soc_kwargs = soc_core_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(integrated_main_ram_size=32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug=True,
**soc_kwargs)
if args.separate_arena:
soc.add_config('SOC_SEPARATE_ARENA')
soc.add_ram(
"arena",
origin=0x60000000,
size=256 * 1024,
)
else:
# size-zero .arena region (linker script needs it)
region = SoCRegion(0x60000000, 0, cached=True, linker=True)
soc.bus.add_region("arena", region)
if args.cfu_mport:
#
# add 4 read-only ports with LSBs fixed to 00, 01, 10, and 11.
# and connect them to the CFU
#
newport = []
for i in range(4):
newport.append(soc.arena.mem.get_port())
soc.specials += newport[i]
p_adr_from_cfu = Signal(14)
p_adr = Cat(Constant(i, 2), p_adr_from_cfu)
p_dat_r = Signal(32)
soc.comb += [
p_dat_r.eq(newport[i].dat_r),
newport[i].adr.eq(p_adr),
]
soc.cpu.cfu_params.update(**{f"o_port{i}_addr": p_adr_from_cfu})
soc.cpu.cfu_params.update(**{f"i_port{i}_din": p_dat_r})
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
def main():
patch_cpu_variant()
parser = argparse.ArgumentParser(description="HPS SoC")
hps_soc_args(parser)
parser.add_argument("--debug",
action="store_true",
help="Enable debug mode")
parser.add_argument(
"--slim_cpu",
action="store_true",
help=
"DEPRECATED: use '--cpu-variant=slim+cfu' instead (Use slimmer VexRiscv (required for mnv2_first))"
)
parser.add_argument(
"--build",
action="store_true",
help="Whether to do a full build, including the bitstream")
parser.add_argument(
"--toolchain",
default="oxide",
help="Which toolchain to use: oxide (default) or radiant")
parser.add_argument(
"--parallel-nextpnr",
action="store_true",
help=
"Whether to use the parallel nextpnr script with the oxide toolchain")
parser.add_argument("--extra-nextpnr-params",
action="store_true",
help="Enable extra nextpnr parameters")
parser.add_argument(
"--synth_mode",
default="radiant",
help="Which synthesis mode to use with Radiant toolchain: "
"radiant/synplify (default), lse, or yosys")
parser.add_argument("--cpu-cfu",
default=None,
help="Specify file containing CFU Verilog module")
parser.add_argument("--cpu-variant",
default=None,
help="Which CPU variant to use")
parser.add_argument("--separate-arena",
action="store_true",
help="Create separate RAM for tensor arena")
parser.add_argument("--cfu-mport",
action="store_true",
help="Create a direct connection between CFU and LRAM")
parser.add_argument(
"--execute-from-lram",
action="store_true",
help=
"Make the CPU execute from integrated ROM stored in LRAM instead of flash"
)
parser.add_argument(
"--integrated-rom-init",
metavar="FILE",
help="Use FILE as integrated ROM data instead of default BIOS")
parser.add_argument("--build-bios",
action="store_true",
help="Flag to specify that the BIOS is built as well")
parser.add_argument("--just-synth",
action='store_true',
help="Stop after synthesis")
parser.add_argument(
"--dynamic-clock-control",
action="store_true",
help=
"Enable dynamic clock control between CPU and CFU to reduce FPGA power consumption."
)
args = parser.parse_args()
if args.integrated_rom_init:
integrated_rom_init = get_mem_data(args.integrated_rom_init, "little")
else:
integrated_rom_init = []
if args.cpu_variant:
variant = args.cpu_variant
elif args.cpu_cfu:
if args.slim_cpu:
variant = "slim+cfu+debug" if args.debug else "slim+cfu"
else:
variant = "full+cfu+debug" if args.debug else "full+cfu"
else:
variant = "full+debug" if args.debug else "full"
copy_cpu_variant_if_needed(variant)
soc = HpsSoC(Platform(args.toolchain, args.parallel_nextpnr,
args.extra_nextpnr_params, args.just_synth),
debug=args.debug,
variant=variant,
cpu_cfu=args.cpu_cfu,
execute_from_lram=args.execute_from_lram,
separate_arena=args.separate_arena,
integrated_rom_init=integrated_rom_init,
build_bios=args.build_bios,
cfu_mport=args.cfu_mport,
dynamic_clock_control=args.dynamic_clock_control)
if not args.build_bios:
# To still allow building libraries needed
# by the HPS software, without the necessity of
# having the BIOS (and its gatware requirements such as the Timer)
# this flag needs to be set to True
soc.integrated_rom_initialized = True
builder = create_builder(soc, args)
builder_kwargs = {}
if args.toolchain == "radiant":
builder_kwargs.update(radiant_build_argdict(args))
elif args.toolchain == "oxide":
builder_kwargs.update(oxide_argdict(args))
vns = builder.build(**builder_kwargs, run=args.build)
soc.do_exit(vns)
if not args.build:
print("Use --build to build the bitstream, if needed")
