def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 12.5e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# FIXME: This is probably too tight?
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk)
self.platform.add_platform_command(
"""
# FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have
# been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
# The clock IOB component <eth_clocks_rx> is placed at site <K15>.
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
# The IOB component <eth_clocks_tx> is placed at site <K16>.
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("eth_clocks"), platform.request("eth"))
self.platform.add_source("gateware/rgmii_if.vhd")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.specials += [
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk),
]
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get(
'cpu_type', 'lm32') == 'or1k':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("eth_clocks"), platform.request("eth"))
self.platform.add_source("gateware/rgmii_if.vhd")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
#self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.cd_eth_rx.clk.attr.add("keep")
self.ethphy.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
self.platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
def __init__(self, phy="rgmii", **kwargs):
assert phy in ["rgmii", "1000basex"]
BaseSoC.__init__(self, **kwargs)
# RGMII Ethernet PHY -----------------------------------------------------------------------
if phy == "rgmii":
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# 1000BaseX Ethernet PHY -------------------------------------------------------------------
if phy == "1000basex":
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk125.p,
i_IB=refclk125.n,
o_O=refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(
qpll.channels[0], self.platform.request("sfp", 0),
self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk,
1e9 / 62.5e6)
self.platform.add_period_constraint(self.ethphy.rxoutclk,
1e9 / 62.5e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.txoutclk,
self.ethphy.rxoutclk)
# Ethernet MAC -----------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq))
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.oled = oled.OLED(platform.request("oled"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region(
"spiflash", self.mem_map["spiflash"], 16*1024*1024)
self.add_interrupt("uart")
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
encoder_port = self.sdram.crossbar.get_port(mode="read", dw=128)
self.submodules.encoder_reader = EncoderDMAReader(encoder_port)
encoder_cdc = stream.AsyncFIFO([("data", 128)], 4)
encoder_cdc = ClockDomainsRenamer({
"write": "sys",
"read": "encoder"
})(encoder_cdc)
encoder_buffer = ClockDomainsRenamer("encoder")(EncoderBuffer())
encoder = Encoder(platform)
encoder_streamer = USBStreamer(platform, platform.request("fx2"))
self.submodules += encoder_cdc, encoder_buffer, encoder, encoder_streamer
self.comb += [
self.encoder_reader.source.connect(encoder_cdc.sink),
encoder_cdc.source.connect(encoder_buffer.sink),
encoder_buffer.source.connect(encoder.sink),
encoder.source.connect(encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
self.platform.add_period_constraint(encoder_streamer.cd_usb.clk, 10.0)
encoder_streamer.cd_usb.clk.attr.add("keep")
self.crg.cd_encoder.clk.attr.add("keep")
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.crg.cd_encoder.clk,
encoder_streamer.cd_usb.clk)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
# sdram
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') != 'lm32':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def add_spi_flash(self):
# TODO: add spiflash1x support
spiflash_pads = self.platform.request("spiflash4x")
self.submodules.spiflash = SpiFlash(
spiflash_pads,
dummy=11,
div=2,
with_bitbang=True,
endianness=self.cpu.endianness)
self.spiflash.add_clk_primitive(self.platform.device)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"], 0x1000000, type="io")
self.add_csr("spiflash")
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# create VGA terminal
self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(mem_decoder(self.mem_map["terminal"]), self.terminal.bus)
self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
# connect VGA pins
vga = self.platform.request('vga_out', 0)
self.comb += [
vga.vsync_n.eq(terminal.vsync),
vga.hsync_n.eq(terminal.hsync),
vga.r.eq(terminal.red[4:8]),
vga.g.eq(terminal.green[4:8]),
vga.b.eq(terminal.blue[4:8])
]
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
eth_clocks = self.platform.request("eth_clocks")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
self.platform.request("eth"), clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# period constraints are required here because of vivado
self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk, eth_clocks.rx)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get(
'cpu_type', 'lm32') != 'lm32':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# FIXME: This is probably too tight?
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk)
self.platform.add_platform_command(
"""
# FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have
# been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
# The clock IOB component <eth_clocks_rx> is placed at site <K15>.
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
# The IOB component <eth_clocks_tx> is placed at site <K16>.
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
self.add_interrupt("ethmac")
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.specials += [
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk)
]
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 40.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self):
arty.EthernetSoC.__init__(self,
cpu_type="vexriscv",
cpu_variant="linux")
self.cpu.use_external_variant("VexRiscv.v")
self.add_constant("NETBOOT_LINUX_VEXRISCV", None)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, 0x4000)
# spiflash
spiflash_pads = self.platform.request("spiflash4x")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=11,
div=2,
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
0x1000000)
self.add_constant("FLASHBOOT_LINUX_VEXRISCV", None)
self.add_constant("FLASH_BOOT_ADDRESS", None)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.add_constant("ETHPHY_MDIO_ADDR", 1)
self.submodules.ethphy = LiteEthPHY(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
period_ns(25e6))
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
period_ns(25e6))
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def add_spi_flash(self):
# FIXME: only support 7-series for now
spiflash_pads = self.platform.request("spiflash4x")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=11,
div=2,
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
0x1000000)
def __init__(self,
platform,
with_sdram_bist=True, bist_async=True, bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
# uart mux
uart_sel = platform.request("user_sw", 0)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
uart_phys = {
"cpu": UARTVirtualPhy(),
"bridge": UARTVirtualPhy()
}
self.comb += [
If(uart_sel,
self.uart_phy.source.connect(uart_phys["bridge"].source),
uart_phys["bridge"].sink.connect(self.uart_phy.sink),
uart_phys["cpu"].source.ready.eq(1) # avoid stalling cpu
).Else(
self.uart_phy.source.connect(uart_phys["cpu"].source),
uart_phys["cpu"].sink.connect(self.uart_phy.sink),
uart_phys["bridge"].source.ready.eq(1) # avoid stalling bridge
)
]
# uart cpu
self.submodules.uart = UART(uart_phys["cpu"])
# uart bridge
self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x8000
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x8000
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
# self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads,
dummy=spiflash_dummy[spiflash],
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
16 * 1024 * 1024)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# sdram
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
controller_settings = ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
with_analyzer=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation", ident_version=True,
with_uart=False,
**kwargs)
# crg
self.submodules.crg = CRG(platform.request("sys_clk"))
# serial
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
# sdram
if with_sdram:
sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings
phy_settings = PhySettings(
memtype="SDR",
dfi_databits=16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0
)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces
# ethernet
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
# etherbone
if with_etherbone:
# eth phy
self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
# eth core
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq)
if with_ethernet:
etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore)
self.submodules.etherbonecore = etherbonecore
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# analyzer
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self,
platform,
with_sdram_bist=True,
bist_async=True,
bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
uart_interfaces = [RS232PHYInterface() for i in range(2)]
self.submodules.uart = UART(uart_interfaces[0])
self.submodules.bridge = WishboneStreamingBridge(
uart_interfaces[1], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.uart_phy = RS232PHY(platform.request("serial"),
self.clk_freq, 115200)
self.submodules.uart_multiplexer = UARTMultiplexer(
uart_interfaces, self.uart_phy)
self.comb += self.uart_multiplexer.sel.eq(
platform.request("user_sw", 0))
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(100e6))
self.submodules.leds = led.ClassicLed(
Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(
self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(
mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(
mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port,
random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base,
16 * 1024 * 1024)
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50",
with_analyzer=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e9/platform.default_clk_period)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation", ident_version=True,
with_uart=False,
**kwargs)
# crg
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# serial
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
# sdram
if with_sdram:
sdram_module = IS42S16160(sys_clk_freq, "1:1")
phy_settings = PhySettings(
memtype="SDR",
dfi_databits=1*16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0
)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_refresh=False))
# reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces
# ethernet
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
# etherbone
if with_etherbone:
# eth phy
self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
# eth core
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq)
if with_ethernet:
etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore)
self.submodules.etherbonecore = etherbonecore
# etherbone
self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# analyzer
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
with_uart=False,
integrated_rom_size=0x10000,
integrated_sram_size=0x10000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk,
period_ns(clk_freq))
self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200)
self.suart.add_uart_pads(platform.request('serial'))
self.submodules.uart = self.suart.uart
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(
with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0,
i_GSR=0,
i_GTS=0,
i_KEYCLEARB=0,
i_PACK=0,
i_USRCCLKO=spiflash_pads.clk,
i_USRCCLKTS=0,
i_USRDONEO=1,
i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(
spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
16 * 1024 * 1024)
if self.cpu_type == "vexriscv" and self.cpu_variant == "linux":
size = 0x4000
self.submodules.emulator_ram = wishbone.SRAM(size)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"],
self.emulator_ram.bus, size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_interrupt("uart")
